Selective Shrinkage of Contact Elements in a Semiconductor Device
    3.
    发明申请
    Selective Shrinkage of Contact Elements in a Semiconductor Device 有权
    半导体器件中接触元件的选择性收缩

    公开(公告)号:US20110291292A1

    公开(公告)日:2011-12-01

    申请号:US13102411

    申请日:2011-05-06

    Abstract: In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element.

    Abstract translation: 在复杂的半导体器件中,可以基于衬垫材料提供连接到形成在其上方的紧密间隔的栅电极结构的有源半导体区域的接触元件,以便减小接触开口的横向宽度,而另一方面, 非临界接触元件可以基于非减小的横向尺寸形成。 为此,临界接触元件的至少第一部分形成并在形成非关键接触元件之前设置有衬垫材料。

    Selective shrinkage of contact elements in a semiconductor device
    6.
    发明授权
    Selective shrinkage of contact elements in a semiconductor device 有权
    半导体器件中接触元件的选择性收缩

    公开(公告)号:US08536050B2

    公开(公告)日:2013-09-17

    申请号:US13102411

    申请日:2011-05-06

    Abstract: In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element.

    Abstract translation: 在复杂的半导体器件中,可以基于衬垫材料提供连接到形成在其上方的紧密间隔的栅电极结构的有源半导体区域的接触元件,以便减小接触开口的横向宽度,而另一方面, 非临界接触元件可以基于非减小的横向尺寸形成。 为此,临界接触元件的至少第一部分形成并在形成非关键接触元件之前设置有衬垫材料。

    Replacement Gate Approach for High-K Metal Gate Stacks Based on a Non-Conformal Interlayer Dielectric
    10.
    发明申请
    Replacement Gate Approach for High-K Metal Gate Stacks Based on a Non-Conformal Interlayer Dielectric 审中-公开
    基于非保形层间介质的高K金属栅极堆叠的替代栅极方法

    公开(公告)号:US20120001263A1

    公开(公告)日:2012-01-05

    申请号:US12970261

    申请日:2010-12-16

    Abstract: In replacement gate approaches for forming sophisticated high-k metal gate electrode structures in a late manufacturing stage, the exposing of the placeholder material may be accomplished on the basis of a substantially uniform interlayer dielectric material, for instance in the form of a silicon nitride material, which may have a similar removal rate compared to the dielectric cap material, the spacer elements and the like of the gate electrode structures. Consequently, a pronounced degree of recessing of the interlayer dielectric material may be avoided, thereby reducing the risk of forming metal residues upon removing any excess material of the gate metal.

    Abstract translation: 在用于在后期制造阶段形成复杂的高k金属栅电极结构的替代栅极方法中,占位符材料的暴露可以基于基本均匀的层间电介质材料来实现,例如以氮化硅材料的形式 ,其可以具有与电介质盖材料相同的去除速率,栅电极结构的间隔元件等。 因此,可以避免层间绝缘材料的显着程度的凹陷,从而降低在去除栅极金属的多余材料时形成金属残留物的风险。

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