公开(公告)号：US08859418B2

公开(公告)日：2014-10-14

申请号：US13348256

申请日：2012-01-11

Applicant: Torsten Huisinga ,  Jens Hahn ,  Kai Frohberg

Inventor： Torsten Huisinga ,  Jens Hahn ,  Kai Frohberg

IPC: H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/31144

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench.

Abstract translation: 本文公开了使用双金属硬掩模积分技术形成导电结构（例如导电线和通孔）的各种方法。 在一个示例中，该方法包括形成第一绝缘材料层，在第一绝缘材料层上方形成第一图案化金属硬掩模层，在第一图案化金属硬掩模层上方形成第二图案化金属硬掩模层， 通过所述第二图案化金属硬掩模层和所述第一图案化金属硬掩模层之间的至少一个蚀刻工艺来限定所述第一绝缘材料层中的沟槽并在所述沟槽中形成导电结构。

公开(公告)号：US08786088B2

公开(公告)日：2014-07-22

申请号：US12966302

申请日：2010-12-13

Applicant: Torsten Huisinga ,  Jens Heinrich ,  Kai Frohberg ,  Frank Feustel

Inventor： Torsten Huisinga ,  Jens Heinrich ,  Kai Frohberg ,  Frank Feustel

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53295 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76808 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses.

Abstract translation: 在复杂的半导体器件中，通过增加优异的机械强度的电介质材料的量，可将复杂的ULK材料与金属线层中的通孔层结合使用，以提高机械稳定性。 由于通孔层的优异的机械稳定性，可以在无铅材料体系的基础上进行用于直接连接半导体管芯和封装衬底的回流工艺，而不会不适当地增加产量损失。

公开(公告)号：US20130178057A1

公开(公告)日：2013-07-11

申请号：US13348256

申请日：2012-01-11

Applicant: Torsten Huisinga ,  Jens Hahn ,  Kai Frohberg

Inventor： Torsten Huisinga ,  Jens Hahn ,  Kai Frohberg

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/31144

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench.

Abstract translation: 本文公开了使用双金属硬掩模积分技术形成导电结构（例如导电线和通孔）的各种方法。 在一个示例中，该方法包括形成第一绝缘材料层，在第一绝缘材料层上方形成第一图案化金属硬掩模层，在第一图案化金属硬掩模层上方形成第二图案化金属硬掩模层， 通过所述第二图案化金属硬掩模层和所述第一图案化金属硬掩模层之间的至少一个蚀刻工艺来限定所述第一绝缘材料层中的沟槽并在所述沟槽中形成导电结构。

公开(公告)号：US08435841B2

公开(公告)日：2013-05-07

申请号：US12975515

申请日：2010-12-22

Applicant: Ralf Richter ,  Torsten Huisinga

Inventor： Ralf Richter ,  Torsten Huisinga

IPC: H01L21/00 ,  H01L29/745

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method of manufacturing a semiconductor device begins by fabricating an n-type metal oxide semiconductor (NMOS) transistor structure on a semiconductor wafer. The method continues by forming an optically reflective layer overlying the NMOS transistor structure, forming a layer of tensile stress inducing material overlying the optically reflective layer, and curing the layer of tensile stress inducing material by applying ultraviolet radiation. Some of the ultraviolet radiation directly radiates the layer of tensile stress inducing material and some of the ultraviolet radiation radiates the layer of tensile stress inducing material by reflecting from the optically reflective layer.

Abstract translation: 半导体器件的制造方法首先在半导体晶片上制造n型金属氧化物半导体（NMOS）晶体管结构。 该方法继续通过形成覆盖在NMOS晶体管结构上的光学反射层，形成覆盖在光学反射层上的拉伸应力诱导材料层，以及通过施加紫外线辐射固化拉伸应力诱导材料层。 一些紫外线辐射直接辐射拉伸应力诱导材料层，一些紫外线辐射通过从光反射层反射而辐射拉伸应力诱导材料层。

公开(公告)号：US20120235304A1

公开(公告)日：2012-09-20

申请号：US13051461

申请日：2011-03-18

Applicant: Torsten Huisinga ,  Ralf Richter ,  Ulrich Mayer

Inventor： Torsten Huisinga ,  Ralf Richter ,  Ulrich Mayer

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L21/76832 ,  H01L21/76825 ,  H01L21/76834 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: Semiconductor devices are formed with a dielectric stack by forming an UV reflecting layer between cured and uncured ULK layers during BEOL processing. Embodiments include forming a first ultra low-k (ULK) layer on a semiconductor element, curing the first ULK layer, forming an ultraviolet (UV) reflecting layer on the first ULK layer, forming a second ULK layer on the UV reflecting layer, and irradiating the second ULK layer with UV light.

Abstract translation: 半导体器件通过在BEOL处理期间在固化和未固化的ULK层之间形成UV反射层而形成有电介质堆叠。 实施例包括在半导体元件上形成第一超低k（ULK）层，固化第一ULK层，在第一ULK层上形成紫外（UV）反射层，在UV反射层上形成第二ULK层，以及 用UV光照射第二ULK层。

公开(公告)号：US20120001343A1

公开(公告)日：2012-01-05

申请号：US12970117

申请日：2010-12-16

Applicant: Torsten Huisinga ,  Michael Grillberger ,  Frank Feustel

Inventor： Torsten Huisinga ,  Michael Grillberger ,  Frank Feustel

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/441

CPC classification number: H01L23/53238 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/53252 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices, densely packed metal line layers may be formed on the basis of an ultra low-k dielectric material, wherein corresponding modified portions of increased dielectric constant may be removed in the presence of the metal lines, for instance, by means of a selective wet chemical etch process. Consequently, the metal lines may be provided with desired critical dimensions without having to take into consideration a change of the critical dimensions upon removing the modified material portion, as is the case in conventional strategies.

Abstract translation: 在复杂的半导体器件中，可以在超低k介电材料的基础上形成密集的金属线层，其中可以在金属线的存在下去除相对于介电常数增加的改性部分，例如通过 选择性湿化学蚀刻工艺。 因此，如在常规策略中的情况那样，金属线可以设置有所需的临界尺寸，而不必考虑去除改性材料部分时临界尺寸的变化。

公开(公告)号：US20120001323A1

公开(公告)日：2012-01-05

申请号：US12966302

申请日：2010-12-13

Applicant: Torsten Huisinga ,  Jens Heinrich ,  Kai Frohberg ,  Frank Feustel

Inventor： Torsten Huisinga ,  Jens Heinrich ,  Kai Frohberg ,  Frank Feustel

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76808 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses.

Abstract translation: 在复杂的半导体器件中，通过增加优异的机械强度的电介质材料的量，可将复杂的ULK材料与金属线层中的通孔层结合使用，以提高机械稳定性。 由于通孔层的优异的机械稳定性，可以在无铅材料体系的基础上进行用于直接连接半导体管芯和封装衬底的回流工艺，而不会不适当地增加产量损失。

公开(公告)号：US07985668B1

公开(公告)日：2011-07-26

申请号：US12948463

申请日：2010-11-17

Applicant: Ralf Richter ,  Torsten Huisinga ,  Jens Heinrich

Inventor： Ralf Richter ,  Torsten Huisinga ,  Jens Heinrich

IPC: H01L21/00

CPC classification number: H01L21/28052 ,  H01L21/28518 ,  H01L29/452 ,  H01L29/665

Abstract: Generally, the present disclosure is directed to a method of removing “weakened” areas of a metal silicide layer during silicide layer formation, thereby reducing the likelihood that material defects might occur during subsequent device manufacturing. One illustrative embodiment includes depositing a first layer of a refractory metal on a surface of a silicon-containing material, and performing first and second heating processes. The method further comprises performing a cleaning process, depositing a second layer of the refractory metal above the silicon-containing material, and performing a third heating process.

Abstract translation: 通常，本公开涉及在硅化物层形成期间去除金属硅化物层的“弱化”区域的方法，从而减少在随后的器件制造期间可能发生材料缺陷的可能性。 一个示例性实施例包括在含硅材料的表面上沉积难熔金属的第一层，以及进行第一和第二加热过程。 所述方法还包括进行清洗过程，在所述含硅材料上方沉积所述难熔金属的第二层，以及执行第三加热过程。

公开(公告)号：US08598714B2

公开(公告)日：2013-12-03

申请号：US12970553

申请日：2010-12-16

Applicant: Torsten Huisinga ,  Michael Grillberger ,  Jens Hahn

Inventor： Torsten Huisinga ,  Michael Grillberger ,  Jens Hahn

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor device, through hole vias or through silicon vias (TSV) may be formed so as to include an efficient stress relaxation mechanism, for instance provided on the basis of a stress relaxation layer, in order to reduce or compensate for stress forces caused by a pronounced change in volume of the conductive fill materials of the through hole vias. In this manner, the high risk of creating cracks and delamination events in conventional semiconductor devices may be significantly reduced.

Abstract translation: 在半导体器件中，可以形成通孔过孔或通过硅通孔（TSV），以便包括例如基于应力松弛层提供的有效的应力松弛机构，以便减少或补偿所引起的应力 通过通孔过孔的导电填充材料的体积显着变化。 以这种方式，可以显着降低在常规半导体器件中产生裂纹和分层事件的高风险。

公开(公告)号：US20130302989A1

公开(公告)日：2013-11-14

申请号：US13466215

申请日：2012-05-08

Applicant: Oisin Kenny ,  Torsten Huisinga

Inventor： Oisin Kenny ,  Torsten Huisinga

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

Abstract: Generally, the present disclosure is directed to methods for reducing line edge roughness in hardmask integration schemes that are used for forming interconnect structures, such as conductive lines and the like. One illustrative method disclosed herein includes, among other things, forming a metal hardmask above a dielectric material and forming a first opening in the metal hardmask, the first opening comprising sidewalls, and the sidewalls having a surface roughness. The disclosed method further includes reducing the surface roughness of the sidewalls, and using the first opening with the sidewalls of reduced surface roughness to form a second opening in the dielectric material.

Abstract translation: 通常，本公开涉及用于减少用于形成互连结构（例如导线等）的硬掩模集成方案中的线边缘粗糙度的方法。 本文公开的一种说明性方法包括在电介质材料之上形成金属硬掩模并在金属硬掩模中形成第一开口，第一开口包括侧壁，并且侧壁具有表面粗糙度。 所公开的方法还包括减小侧壁的表面粗糙度，并且使用具有减小的表面粗糙度的侧壁的第一开口在电介质材料中形成第二开口。