公开(公告)号：US09281200B2

公开(公告)日：2016-03-08

申请号：US13189997

申请日：2011-07-25

Applicant: Hans-Juergen Thees ,  Sven Beyer ,  Martin Mazur ,  Steffen Laufer

Inventor： Hans-Juergen Thees ,  Sven Beyer ,  Martin Mazur ,  Steffen Laufer

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L21/28123 ,  H01L21/265 ,  H01L21/28035 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4916

Abstract: When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

Abstract translation: 当形成晶体管的复杂的基于半导体的栅极电极结构时，一种类型的栅极电极结构的预掺杂可以在通过使用适当的掩模或填充材料覆盖活性区域并使用 光刻面具 以这种方式，在选择适当的图案化状态方面提供了高度的柔性，同时获得了任何类型的栅电极结构的均匀和优异的横截面形状。

公开(公告)号：US20090274981A1

公开(公告)日：2009-11-05

申请号：US12113559

申请日：2008-05-01

Applicant: Uwe Griebenow ,  Martin Mazur ,  Wolfram Grundke ,  Andre Poock

Inventor： Uwe Griebenow ,  Martin Mazur ,  Wolfram Grundke ,  Andre Poock

IPC: G03F7/20

CPC classification number: G01N21/956 ,  G01N2021/95676 ,  G03F1/84

Abstract: Mask defects, such as crystal growth defects and the like, may be efficiently detected and estimated at an early stage of their development by generating test images of the mask under consideration and inspecting the images on the basis of wafer inspection techniques in order to identify repeatedly occurring defects. In some illustrative embodiments, the exposure process for generating the mask images may be performed on the basis of different exposure parameters, such as exposure doses, in order to enhance the probability of detecting defects and also estimating the effect thereof depending on the varying exposure parameters. Consequently, increased reliability may be achieved compared to conventional direct mask inspection techniques.

Abstract translation: 通过产生所考虑的掩模的测试图像并且在晶片检查技术的基础上检查图像以便重复地识别掩模缺陷，例如晶体生长缺陷等，可以在其显影的早期阶段被有效地检测和估计 发生缺陷。 在一些说明性实施例中，用于产生掩模图像的曝光过程可以基于不同的曝光参数（例如曝光剂量）来执行，以增强检测缺陷的可能性，并且还根据变化的曝光参数来估计其效果 。 因此，与传统的直接掩模检查技术相比，可以实现增加的可靠性。

公开(公告)号：US07547561B2

公开(公告)日：2009-06-16

申请号：US11281997

申请日：2005-11-17

Applicant: Uwe Schulze ,  Martin Mazur ,  Andreas Becker

Inventor： Uwe Schulze ,  Martin Mazur ,  Andreas Becker

IPC: H01L21/66 ,  H01L21/312 ,  H01L21/47

CPC classification number: H01L22/20 ,  Y10S430/136

Abstract: An advanced process control (APC) architecture comprising a process model that incorporates a target offset term is provided. The APC architecture may be applied to a so-called develop inspect critical dimension (DICD) model using the target offset term to correct at least one exposure parameter on the occurrence of an abrupt event. A corresponding event may, for example, concern a modified reflectivity of processed substrates, for example due to a rework of substrates covered by amorphous carbon material.

Abstract translation: 提供了包括包含目标偏移项的过程模型的高级过程控制（APC）架构。 APC架构可以应用于所谓的开发检查关键维度（DICD）模型，使用目标偏移项来校正突发事件发生时的至少一个曝光参数。 相应的事件例如可能涉及经处理的基板的改进的反射率，例如由于由无定形碳材料覆盖的基板的返修。

公开(公告)号：US06649525B1

公开(公告)日：2003-11-18

申请号：US10050485

申请日：2002-01-16

Applicant: Khoi A. Phan ,  Jeffrey Erhardt ,  Jerry Cheng ,  Richard J. Bartlett ,  Anthony P. Coniglio ,  Wolfram Grundke ,  Carol M. Bradway ,  Daniel E. Sutton ,  Martin Mazur

Inventor： Khoi A. Phan ,  Jeffrey Erhardt ,  Jerry Cheng ,  Richard J. Bartlett ,  Anthony P. Coniglio ,  Wolfram Grundke ,  Carol M. Bradway ,  Daniel E. Sutton ,  Martin Mazur

IPC: H01L21461

CPC classification number: G03F7/16 ,  G03F7/30 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/32139

Abstract: Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein. The method may comprise employing an anti reflective coating prior to applying a photo resist coating in a semiconductor manufacturing process. Also disclosed are methodologies for exhausting resist residue during development via a rinsing fluid.

Abstract translation: 公开了用于减少半导体制造工艺中的抗蚀剂残留缺陷的方法和系统。 这些方法包括硬件，衬底，抗蚀剂，显影剂和工艺变量的适当调整，以便从半导体衬底结构去除抗蚀剂残留物，以减少其中的抗蚀剂残留缺陷。 该方法可以包括在半导体制造工艺中施加光致抗蚀剂涂层之前采用抗反射涂层。 还公开了通过冲洗流体在显影期间排出抗蚀剂残留物的方法。

公开(公告)号：US08927407B2

公开(公告)日：2015-01-06

申请号：US13354739

申请日：2012-01-20

Applicant: Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

Inventor： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

IPC: H01L21/28

CPC classification number: H01L21/76897 ,  H01L29/66545

Abstract: Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

Abstract translation: 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

公开(公告)号：US08716120B2

公开(公告)日：2014-05-06

申请号：US13489539

申请日：2012-06-06

Applicant: Klaus Hempel ,  Andy Wei ,  Martin Mazur

Inventor： Klaus Hempel ,  Andy Wei ,  Martin Mazur

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/823842

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing an upper portion of the final work function metal, for instance a titanium nitride material in P-channel transistors. In some illustrative embodiments, the selective removal of the metal-containing electrode material in an upper portion of the gate opening may be accomplished without unduly increasing overall process complexity.

Abstract translation: 当在更换栅极方法的基础上形成复杂的高k金属栅电极结构时，填充高导电电极金属（例如铝）时的填充条件可以通过去除最终功函数金属的上部来增强， 例如P沟道晶体管中的氮化钛材料。 在一些说明性实施例中，可以在门开口的上部中选择性地去除含金属的电极材料，而不会过度增加整个工艺的复杂性。

公开(公告)号：US20130189833A1

公开(公告)日：2013-07-25

申请号：US13354739

申请日：2012-01-20

Applicant: Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

Inventor： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

IPC: H01L21/28

CPC classification number: H01L21/76897 ,  H01L29/66545

Abstract: Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

Abstract translation: 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

公开(公告)号：US20120156865A1

公开(公告)日：2012-06-21

申请号：US13189997

申请日：2011-07-25

Applicant: Hans-Juergen Thees ,  Sven Beyer ,  Martin Mazur ,  Steffen Laufer

Inventor： Hans-Juergen Thees ,  Sven Beyer ,  Martin Mazur ,  Steffen Laufer

IPC: H01L21/28

CPC classification number: H01L21/28123 ,  H01L21/265 ,  H01L21/28035 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4916

Abstract: When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

Abstract translation: 当形成晶体管的复杂的基于半导体的栅极电极结构时，一种类型的栅极电极结构的预掺杂可以在通过使用适当的掩模或填充材料覆盖活性区域并使用 光刻面具 以这种方式，在选择适当的图案化状态方面提供了高度的柔性，同时获得了任何类型的栅电极结构的均匀和优异的横截面形状。

公开(公告)号：US07994059B2

公开(公告)日：2011-08-09

申请号：US11865796

申请日：2007-10-02

Applicant: Ralf Richter ,  Martin Gerhardt ,  Martin Mazur ,  Joerg Hohage

Inventor： Ralf Richter ,  Martin Gerhardt ,  Martin Mazur ,  Joerg Hohage

IPC: H01L21/331

CPC classification number: H01L29/7833 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/7843

Abstract: By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.

Abstract translation: 通过在对具有不同的本征应力的介电衬垫进行图案化之后形成附加的应力介电材料，可以获得在晶体管中性能的显着提高，同时在高比例尺度的半导体器件中形成各个接触开口期间基本上不会构图不均匀性。 附加介电层可以被提供任何类型的固有应力，而不管先前选择的图案化序列如何。

公开(公告)号：US20080078738A1

公开(公告)日：2008-04-03

申请号：US11733350

申请日：2007-04-10

Applicant: Ralf Richter ,  Joerg Hohage ,  Martin Mazur

Inventor： Ralf Richter ,  Joerg Hohage ,  Martin Mazur

IPC: H01B13/00

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/76802

Abstract: By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.

Abstract translation: 通过在溅射蚀刻期间结合在处理室的室壁上表现出高粘附性的材料，可以显着地减少基于ARC层的图案化顺序中的缺陷率，因为粘合材料可以在溅射预清洗期间可靠地暴露 处理。 相应的粘合层可以定位在ARC层堆叠内，以便至少部分地可靠地消耗，同时仍然提供所需的光学特性。 因此，可以实现低缺陷率与高工艺效率的组合。