公开(公告)号：US20240021586A1

公开(公告)日：2024-01-18

申请号：US17812300

申请日：2022-07-13

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H01L25/07 ,  H01L25/00

CPC classification number: H01L25/074 ,  H01L25/50 ,  H01L24/80

Abstract: A stacked gate-all-around (GAA) complementary field-effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA ITT includes at least one three-dimensional (3D) semiconductor slab with a channel region and a first surface. A first gate structure surrounds the channel region in the first GAA FET, and a second gate structure surrounds the channel region in the second GAA FET. The first gate structure is stacked opposite the second gate structure in a direction orthogonal to the first surface. In some examples, a first crystal structure of the 3D semiconductor slab in the first GAA FET has a first orientation, and a second crystal structure of the 3D semiconductor slab in the second GAA FET has a different orientation for improved carrier mobility.

公开(公告)号：US11744059B2

公开(公告)日：2023-08-29

申请号：US16712063

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H10B10/00 ,  H01L29/66 ,  G11C11/412 ,  H01L29/78 ,  H01L27/02

CPC classification number: H10B10/12 ,  G11C11/412 ,  H01L27/0207 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.

公开(公告)号：US11545404B2

公开(公告)日：2023-01-03

申请号：US16868147

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

Abstract: Before a semiconductor die of a brittle III-V compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

公开(公告)号：US11222952B2

公开(公告)日：2022-01-11

申请号：US16749897

申请日：2020-01-22

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Haining Yang ,  Xia Li

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/201 ,  H01L29/66 ,  H01L29/78 ,  H01L29/43

Abstract: A semiconductor device comprising an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor and a P-type metal oxide semiconductor (PMOS) GAA transistor with high charge mobility channel materials is disclosed. The semiconductor device may include a substrate. The semiconductor device may also include an NMOS GAA transistor on the substrate, wherein the NMOS GAA transistor comprises a first channel material. The semiconductor device may further include a PMOS GAA transistor on the substrate, wherein the PMOS GAA transistor comprises a second channel material. The first channel material may have an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material may have a hole mobility greater than a hole mobility of Si.

公开(公告)号：US11177065B2

公开(公告)日：2021-11-16

申请号：US16835227

申请日：2020-03-30

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Xiaoju Yu ,  Xia Li ,  Bin Yang

IPC: H01L23/498 ,  H01F27/22 ,  H01G4/33 ,  H01F27/29 ,  H01G4/252

Abstract: Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.

公开(公告)号：US10886266B1

公开(公告)日：2021-01-05

申请号：US16511099

申请日：2019-07-15

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L27/06 ,  H01L29/93 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H03F3/195 ,  H01L29/66 ,  H01L21/02

Abstract: Aspects generally relate to a P−N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with different materials forming various layers of the varactor and HEMT. Using different material stack-up to form the varactor and HEMT allows characteristics of the varactor and HEMT to be varied for improved performance in different operating scenarios. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.

公开(公告)号：US20200251582A1

公开(公告)日：2020-08-06

申请号：US16266267

申请日：2019-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Gengming Tao ,  Bin Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure generally relate to a high electron mobility transistor and techniques for fabricating the same. Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate; a channel region having a fin disposed above the substrate; a first barrier layer disposed adjacent to a first side and a second side of the first fin, wherein the first side and the second side of the first fin are opposite sides, the first barrier layer forming a heterojunction with the fin; a first dielectric layer disposed adjacent to a first side and a second side of the first barrier layer, wherein the first side and the second side of the first barrier layer are opposite sides; and a first gate region disposed adjacent to the first dielectric layer.

公开(公告)号：US10672807B1

公开(公告)日：2020-06-02

申请号：US16231115

申请日：2018-12-21

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao

IPC: H01L27/144 ,  H01L31/0232 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/103 ,  H01L31/18 ,  H01L31/0216 ,  H01L31/028

Abstract: A photo detector comprises a first photo diode configured to capture visible light, a second photo diode configured to capture one of infrared light or ultraviolet light, and an isolation region between the first photo diode and the second photo diode. The photo detector is capable of capturing infrared light and ultraviolet light in addition to visible light.

公开(公告)号：US20200152739A1

公开(公告)日：2020-05-14

申请号：US16189855

申请日：2018-11-13

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Ye Lu

IPC: H01L29/08 ,  H01L29/24 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L21/768 ,  H01L21/02

Abstract: A transistor comprises a substrate, a first buffer layer on the substrate, a source region, a drain region, and a channel region on the first buffer layer, a gate on the channel region, a source contact, and a drain contact. The source contact is configured to contact at least three sides of the source region and the drain contact is configured to contact at least three sides of the drain region to lower contact resistance in the source region and in the drain region.

公开(公告)号：US10482929B2

公开(公告)日：2019-11-19

申请号：US15817441

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: G11C16/04 ,  G11C5/02 ,  G06N3/08 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/16 ,  G11C11/22 ,  G11C11/54 ,  G11C13/00

Abstract: Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.