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    INTEGRATED CIRCUITS HAVING REDUCED DIMENSIONS BETWEEN COMPONENTS
    81.
    发明申请
    INTEGRATED CIRCUITS HAVING REDUCED DIMENSIONS BETWEEN COMPONENTS 有权
    在组件之间具有减小尺寸的集成电路

    公开(公告)号：US20160372414A1

    公开(公告)日：2016-12-22

    申请号：US14744912

    申请日：2015-06-19

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Da Yang

    IPC: H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234

    CPC classification number: H01L23/528 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211

    Abstract: In a particular aspect, an integrated circuit includes a first transistor including a first source region and a first drain region. The integrated circuit includes a second transistor including a second source region and a second drain region. The integrated circuit includes a first gate structure coupled to the first transistor and to the second transistor. The first gate structure is included in a first layer. The integrated circuit further includes a first metal line coupled to the first source region and to the second drain region. The first metal line has a two-dimensional routing arrangement and is included in a second layer that is distinct from the first layer.

    Abstract translation: 在特定方面，集成电路包括包括第一源极区域和第一漏极区域的第一晶体管。 集成电路包括包括第二源区和第二漏区的第二晶体管。 集成电路包括耦合到第一晶体管和第二晶体管的第一栅极结构。 第一栅极结构被包括在第一层中。 集成电路还包括耦合到第一源极区域和第二漏极区域的第一金属线路。 第一金属线具有二维布线布置，并且包括在与第一层不同的第二层中。

    Systems and methods of forming a reduced capacitance device
    83.
    发明授权
    Systems and methods of forming a reduced capacitance device 有权
    形成减电容器件的系统和方法

    公开(公告)号：US09472453B2

    公开(公告)日：2016-10-18

    申请号：US14471086

    申请日：2014-08-28

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

    IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/76879 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76885

    Abstract: A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance.

    Abstract translation: 一种方法包括形成包括衬底，氧化物层和第一低k层的电子器件结构。 该方法还包括通过图案化氧化物层来形成开口，用导电材料填充开口以在开口内形成导电结构，以及使用第一低k层作为蚀刻停止层去除氧化物层。 导电结构接触第一低k层。 去除氧化物层包括相对于氧化物层执行化学气相蚀刻工艺以形成蚀刻副产物并除去蚀刻副产物。 该方法包括使用使第二低k层限定一个或多个空腔的沉积工艺形成第二低k层。 每个空腔限定在第一导电结构和相邻的导电结构之间，第一和第二导电结构之间具有小于阈值距离的间隔。

    Shared global read and write word lines
    84.
    发明授权
    Shared global read and write word lines 有权
    共享全局读写字线

    公开(公告)号：US09455026B2

    公开(公告)日：2016-09-27

    申请号：US14546980

    申请日：2014-11-18

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Ping Liu ,  Kern Rim ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/419 ,  G11C8/14 ,  H01L27/06 ,  G11C8/16

    CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0688 ,  H01L27/1104

    Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

    Abstract translation: 一种装置包括包括第一行位单元和第二行位单元的位单元阵列。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第一全局读取字线。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第二全局读取字线。 该装置还包括全局写入字线，其被配置为选择性地耦合到第一行位单元和第二行位单元。 第一个全局读取字线，第二个全局读取字线和全局写入字线位于公共金属层中。

    TIE-OFF STRUCTURES FOR MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS, AND RELATED METHODS
    86.
    发明申请
    TIE-OFF STRUCTURES FOR MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS, AND RELATED METHODS 审中-公开
    中间线（MOL）制造集成电路的TIE-OFF结构及相关方法

    公开(公告)号：US20160079167A1

    公开(公告)日：2016-03-17

    申请号：US14484353

    申请日：2014-09-12

    Applicant: QUALCOMM Incorporated

    Inventor： John Jianhong Zhu ,  Kern Rim ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu

    IPC: H01L23/535 ,  H01L21/768 ,  H01L27/06

    CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Tie-off structures for middle-of-line (MOL) manufactured integrated circuits, and related methods are disclosed. As a non-limiting example, the tie-off structure may be used to tie-off a drain or source of a transistor to the gate of the transistor, such as provided in a dummy gate used for isolation purposes. In this regard in one aspect, a MOL stack is provided that includes a metal gate connection that is coupled to a metal layer through metal structure disposed in and above a dielectric layer above a gate associated with the metal gate connection. By coupling the metal gate connection to the metal layer, the gate of a transistor may be coupled or “tied-off” to a source or drain element of the transistor. This may avoid the need to etch the metal gate connection provided below the dielectric layer to provide sufficient connectivity between the metal layer and the metal gate connection.

    Abstract translation: 公布了中线（MOL）制造集成电路的结合结构及相关方法。 作为非限制性示例，可以使用结合结构将晶体管的漏极或源极结合到晶体管的栅极，例如在用于隔离目的的虚拟栅极中提供。 在这方面，在一方面，提供了一种MOL堆叠，其包括金属栅极连接，金属栅极连接通过设置在与金属栅极连接相关联的栅极上方的电介质层中和上方的金属结构耦合到金属层。 通过将金属栅极连接耦合到金属层，晶体管的栅极可以耦合或“截止”到晶体管的源极或漏极元件。 这可以避免需要蚀刻在介电层下方提供的金属栅极连接，以在金属层和金属栅极连接之间提供足够的连通性。

    SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE
    87.
    发明申请
    SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE 有权
    SILICON GERMANIUM读端口，用于静态随机存取存储器寄存器文件

    公开(公告)号：US20160064068A1

    公开(公告)日：2016-03-03

    申请号：US14473974

    申请日：2014-08-29

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C11/405 ,  G11C11/409 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054

    Abstract: A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.

    Abstract translation: 静态随机存取存储器（SRAM）电路包括耦合到写入端口的写入端口和读取端口。 读端口包括读位线和具有硅锗（SiGe）沟道的第一p型金属氧化物半导体（PMOS）晶体管。 读端口还包括具有第二SiGe沟道的第二PMOS晶体管，其中第二PMOS晶体管耦合到第一PMOS晶体管。

    Via material selection and processing
    89.
    发明授权
    Via material selection and processing 有权
    通过材料选择和处理

    公开(公告)号：US09196583B1

    公开(公告)日：2015-11-24

    申请号：US14274470

    申请日：2014-05-09

    Applicant: QUALCOMM Incorporated

    Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Kern Rim ,  Zhongze Wang

    IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5228 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.

    Abstract translation: 用于半导体互连的半导体互连和方法。 互连可以包括在第一导电互连层和第一中间线（MOL）互连层之间的第一导电材料的第一通孔。 第一个MOL互连层位于第一层。 第一个通孔用单个镶嵌工艺制造。 这种半导体互连还包括在第一导电互连层和第二MOL互连层之间的第二导电材料的第二通孔。 第二个MOL互连层位于第二层。 第二个通孔用双镶嵌工艺制造。 第一导电材料与第二导电材料不同。

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