公开(公告)号：US10591790B2

公开(公告)日：2020-03-17

申请号：US15807451

申请日：2017-11-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yongda Ma ,  Pan Li

IPC: G02F1/1362 ,  G02F1/1343 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66

Abstract: An array substrate and a display device are provided, which relate to the field of display and are for alleviating or mitigating the problem of bad contact between the pixel electrode and the drain pad caused by deep via holes. The array substrate includes a plurality of pixel units, each including a drain pad, a pixel electrode and an insulating layer above the drain pad. The drain pad has a first via hole, and the insulating layer has a second via hole that exposes at least a portion of the first via hole and a portion of the drain pad around the first via hole. The pixel electrode extends along an inner wall of the second via hole and contacts the exposed portion of the drain pad.

公开(公告)号：US10431669B2

公开(公告)日：2019-10-01

申请号：US15116980

申请日：2015-10-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaolong Li ,  Zheng Liu ,  Xiaoyong Lu ,  Dong Li ,  Chunping Long

IPC: H01L29/66 ,  H01L21/20 ,  H01L21/265 ,  H01L21/28 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786

Abstract: A manufacturing method for a polysilicon thin film is provided. The manufacturing method for a polysilicon thin film includes forming a polysilicon layer, treating a surface of the polysilicon layer so that the surface of the polysilicon layer is electronegative, and supplying polar gas into a process chamber so that polar molecules of the polar gas are adsorbed on the surface of the polysilicon layer which is electronegative so as to form the polysilicon thin film, a surface of which has a hole density higher than an electron density.

公开(公告)号：US10317751B2

公开(公告)日：2019-06-11

申请号：US15791376

申请日：2017-10-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yongda Ma

IPC: G02F1/1343 ,  G02F1/1337 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/417 ,  H01L27/32 ,  H01L21/77 ,  G02F1/136

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes: first common electrode lines; gate lines; a gate insulation layer; data lines, the first common electrode lines crossing the data lines to define a plurality of pixel units, each gate line dividing a corresponding pixel unit into two sub-regions, a separate TFT being arranged at each sub-region; second common electrode lines; and a drain electrode pad arranged at each sub-region and a drain electrode connection line for connecting the drain electrode pad to a drain electrode of the TFT. The drain electrode pad, the drain electrode connection line and the drain electrode are arranged at an identical layer. An orthogonal projection of each second common electrode line onto the base substrate overlaps an orthogonal projection of the drain electrode pad onto the base substrate.

公开(公告)号：US10262572B2

公开(公告)日：2019-04-16

申请号：US14778039

申请日：2015-03-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Ying Wang

IPC: G09G3/00 ,  G09G3/36 ,  G09G3/32 ,  G11C19/28 ,  G06F3/041 ,  G09G3/20 ,  G11C19/18

Abstract: GOA driving unit includes an input end, a starting module, a control module, an output module and a gate driving signal output end. The starting module is configured to, within a starting time period, input a triggering signal from the input end into the control module under the control of a first clock signal. The control module is configured to, within an output time period, output a second clock signal to the output module. The output module is configured to output a first level to the gate driving signal output end within the starting time period, output the second clock signal to the gate driving signal output end within the output time period, and output the first level to the gate driving signal output end within a maintenance time period. The first clock signal is of a phase reverse to the second clock signal.

公开(公告)号：US20180211976A1

公开(公告)日：2018-07-26

申请号：US15718973

申请日：2017-09-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long

IPC: H01L27/12 ,  H01L23/64

CPC classification number: H01L27/124 ,  H01L23/64

Abstract: Embodiments of the disclosure relate to a signal line structure, an array substrate, and a display device, where the signal line structure includes a plurality of signal lines arranged adjacent to each other at the same layer; and at least one redundant wire at a different layer from the signal lines, wherein each redundant wire corresponds to two adjacent signal lines, and a positive projection of the each redundant wire onto the layer where the signal lines are located covers a part or all of a gap between the two adjacent signal lines corresponding to the each redundant wire.

公开(公告)号：US20170271171A1

公开(公告)日：2017-09-21

申请号：US15321537

申请日：2016-03-07

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoyong Lu ,  Chunping Long ,  Chien Hung Liu ,  Yucheng Chan ,  Xiaolong Li ,  Zheng Liu

IPC: H01L21/321 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L21/3212 ,  B81C2201/0121 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/48 ,  H01L21/7684

Abstract: Embodiments of the present invention provide a method of processing a surface of a polysilicon and a method of processing a surface of a substrate assembly. The method of processing a surface of a polysilicon includes forming a material film on the surface of the polysilicon; and processing, by using a chemico-mechanical polishing technology, the surface of the polysilicon on which the material film is formed. The material film is selected such that the polysilicon is preferentially removed in a polishing process.

公开(公告)号：US09437417B2

公开(公告)日：2016-09-06

申请号：US14081833

申请日：2013-11-15

Applicant: Boe Technology Group Co., Ltd.

Inventor： Xueyan Tian ,  Chunping Long

IPC: H01L21/31 ,  H01L21/02 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L27/1281 ,  H01L21/02112 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02672 ,  H01L21/02686 ,  H01L27/1262 ,  H01L29/66757 ,  H01L29/78675

Abstract: A method for producing a low temperature polycrystalline silicon thin film, comprising steps of: providing a substrate; forming a thermal conduction and electrical insulation layer, a buffer layer and an amorphous silicon layer on the substrate in this order; and performing a high-temperature treatment and a laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film, wherein the thermal conduction and electrical insulation layer comprises regular patterns distributed on the substrate.

Abstract translation: 一种生产低温多晶硅薄膜的方法，包括以下步骤：提供基底; 在该基板上依次形成导热和电绝缘层，缓冲层和非晶硅层; 以及对所述非晶硅层进行高温处理和激光退火以将所述非晶硅层转换为多晶硅薄膜，其中所述导热和电绝缘层包括分布在所述基板上的规则图案。

公开(公告)号：US09040988B2

公开(公告)日：2015-05-26

申请号：US13963372

申请日：2013-08-09

Applicant: Boe Technology Group Co., Ltd.

Inventor： Zheng Liu ,  Chunping Long ,  Pil Seok Kim

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/66

CPC classification number: H01L29/78669 ,  H01L29/66757 ,  H01L29/66765

Abstract: The disclosure discloses a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which can manufacture a thin film transistor with lower contents of impurity at a low temperature. The thin film transistor comprises: a substrate, and an active layer disposed on the substrate, the active layer comprising a source region, a drain region and a channel region, wherein the active layer is formed by depositing an inducing metal on an amorphous silicon layer on the substrate by an atomic layer deposition (ALD) method and then conducting heat treatment on the amorphous silicon layer deposited with the inducing metal so that metal induction crystallization and metal induction lateral crystallization take place in the amorphous silicon layer.

Abstract translation: 本发明公开了一种薄膜晶体管及其制造方法，阵列基板和显示装置，其可以在低温下制造具有较低杂质含量的薄膜晶体管。 所述薄膜晶体管包括：衬底和设置在所述衬底上的有源层，所述有源层包括源极区，漏极区和沟道区，其中所述有源层通过在非晶硅层上沉积诱导金属而形成 通过原子层沉积（ALD）方法在衬底上，然后对沉积有诱导金属的非晶硅层进行热处理，使得金属诱导结晶和金属诱导横向结晶发生在非晶硅层中。

公开(公告)号：US20140065804A1

公开(公告)日：2014-03-06

申请号：US13980478

申请日：2012-12-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xueyan Tian ,  Chunping Long ,  Jiangfeng Yao

IPC: H01L21/02

CPC classification number: H01L21/02502 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/56 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/268 ,  H01L21/32055

Abstract: An embodiment of the present invention relates to a low temperature polysilicon thin film and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer on a substrate (S11); forming a seed layer comprising a plurality of uniformly distributed crystal nuclei on the buffer layer by using a patterning process (S12); forming an amorphous silicon layer on the seed layer (S13); and performing an excimer laser annealing process on the amorphous silicon layer (S14).

Abstract translation: 本发明的实施例涉及一种低温多晶硅薄膜及其制造方法。 制造方法包括：在基板上形成缓冲层（S11）; 通过图案化工艺在缓冲层上形成包含多个均匀分布的晶核的晶种层（S12）; 在籽晶层上形成非晶硅层（S13）; 对非晶硅层进行准分子激光退火处理（S14）。

公开(公告)号：US11901354B2

公开(公告)日：2024-02-13

申请号：US17255978

申请日：2020-06-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Hui Li

IPC: H01L27/12 ,  H01L27/02

CPC classification number: H01L27/0251 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259

Abstract: The disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate includes a plurality of conductive lines and an electrostatic protection circuit on a base substrate. At least some of the conductive lines are connected through the electrostatic protection circuit. Two conductive lines connected with the electrostatic protection circuit are respectively a first conductive line and a second conductive line. The electrostatic protection circuit includes a first transistor, a second transistor, and a first capacitor. A first electrode of the first transistor, a first electrode of the second transistor and a gate electrode of the second transistor are connected to the second conductive line, and a second electrode of the first transistor, a second electrode of the second transistor and a gate electrode of the first transistor are connected to the first conductive line.