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    Head electrode region for a reliable metal-to-metal contact micro-relay MEMS switch
    3.
    发明授权
    Head electrode region for a reliable metal-to-metal contact micro-relay MEMS switch 有权
    头电极区域用于可靠的金属 - 金属接触微型继电器MEMS开关

    公开(公告)号：US07352266B2

    公开(公告)日：2008-04-01

    申请号：US10994704

    申请日：2004-11-20

    申请人： Chia-Shing Chou

    发明人： Chia-Shing Chou

    IPC分类号： H01H51/22

    CPC分类号： B81C1/00611 ,  B81C2201/0121 ,  H01H59/0009 ,  H01H2059/0072 ,  Y10T29/49105

    摘要： A head electrode region for an electromechanical device is presented, comprising a first insulating layer having electrode region edges; and a head electrode, where the head electrode comprises a locking portion, with the locking portion surrounding the electrode region edges of the first insulating layer such that the head electrode is held fixed relative to the first insulating layer. The head electrode region can further comprise a top region residing above the first insulating layer and a contact region residing below the first insulator, the head electrode region further comprising a second insulating layer formed to cover at least a portion of the top region of the head electrode.

    摘要翻译： 本发明提供了一种机电装置的头电极区域，包括具有电极区域边缘的第一绝缘层; 以及头电极，其中所述头电极包括锁定部分，所述锁定部分围绕所述第一绝缘层的电极区域边缘，使得所述头电极相对于所述第一绝缘层保持固定。 磁头电极区域可以进一步包括位于第一绝缘层上方的顶部区域和位于第一绝缘体下方的接触区域，所述磁头电极区域还包括形成为覆盖磁头的顶部区域的至少一部分的第二绝缘层 电极。

    Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
    4.
    发明授权
    Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation 有权
    使用至少一个调制掺杂量子阱结构和一个或多个蚀刻停止层来制造半导体器件以准确接触形成的方法

    公开(公告)号：US07101724B2

    公开(公告)日：2006-09-05

    申请号：US10994703

    申请日：2004-11-20

    申请人： Chia-Shing Chou

    发明人： Chia-Shing Chou

    IPC分类号： H01L21/20

    CPC分类号： B81C1/00611 ,  B81C2201/0121 ,  H01H59/0009 ,  H01H2059/0072 ,  Y10T29/49105

    摘要： The present invention relates to MEM switches. More specifically, the present invention relates to a system and method for making MEM switches having a common ground plane. One method for making MEM switches includes: patterning a common ground plane layer on a substrate; forming a dielectric layer on the common ground plane layer; depositing a DC electrode region through the dielectric layer to contact the common ground plane layer; and depositing a conducting layer on the DC electrode region so that regions of the conducting layer contact the DC electrode region, so that the common ground plane layer provides a common ground for the regions of the conducting layer.

    摘要翻译： 本发明涉及MEM开关。 更具体地，本发明涉及一种用于制造具有公共接地层的MEM开关的系统和方法。 制造MEM开关的一种方法包括：在衬底上构图公共接地层; 在公共接地层上形成介电层; 通过所述电介质层沉积DC电极区域以接触所述公共接地层; 以及在所述直流电极区域上沉积导电层，使得所述导电层的区域接触所述直流电极区域，使得所述公共接地层提供所述导电层的区域的公共接地。

    Method for producing optically planar surfaces for micro-electromechanical system devices
    6.
    发明申请
    Method for producing optically planar surfaces for micro-electromechanical system devices 有权
    微机电系统装置的光学平面的制造方法

    公开(公告)号：US20010029058A1

    公开(公告)日：2001-10-11

    申请号：US09867928

    申请日：2001-05-30

    申请人： Eastman Kodak Company

    发明人： Joseph Jech JR. ,  John A. Lebens ,  John C. Brazas JR. ,  Marek W. Kowarz

    IPC分类号： H01L021/00 ,  H01L031/0232

    CPC分类号： B81C1/00611 ,  B81C2201/0121

    摘要： A method for producing optically planar surfaces for micro-electromechanical system devices (MEMS), comprising the steps of: depositing a first layer over a substrate; forming a channel in the first layer wherein the channel has a depth defined by a thickness of the first layer and a width greater than 10 microns; depositing a second layer over the first layer wherein the second layer has a thickness greater than the depth of the channel and is composed of a different material than the first layer; removing the second layer from outside the channel leaving an overlap at the edge of the channel; and polishing the second layer that fills the channel to obtain an optically planar surface for the MEMS device.

    摘要翻译： 一种用于制造用于微机电系统装置（MEMS）的光学平面的方法，包括以下步骤：在衬底上沉积第一层; 在第一层中形成通道，其中通道具有由第一层的厚度和大于10微米的宽度限定的深度; 在所述第一层上沉积第二层，其中所述第二层的厚度大于所述沟道的深度，并且由与所述第一层不同的材料构成; 从所述通道外部移除所述第二层，在所述通道的边缘处留下重叠; 并抛光填充通道的第二层以获得用于MEMS器件的光学平面表面。

    Process for filling etched holes
    10.
    发明授权
    Process for filling etched holes 有权

    公开(公告)号：US09708183B2

    公开(公告)日：2017-07-18

    申请号：US15046239

    申请日：2016-02-17

    申请人： Memjet Technology Ltd.

    发明人： Angus North ,  Ronan O'Reilly ,  Gregory McAvoy

    IPC分类号： B81C1/00 ,  B41J2/16

    CPC分类号： B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

    摘要： A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.