公开(公告)号：US20050254289A1

公开(公告)日：2005-11-17

申请号：US11171323

申请日：2005-07-01

Applicant: Kentaro Nakajima ,  Minoru Amano ,  Tomomasa Ueda ,  Shigeki Takahashi

Inventor： Kentaro Nakajima ,  Minoru Amano ,  Tomomasa Ueda ,  Shigeki Takahashi

IPC: H01L27/105 ,  C23F4/00 ,  G11C11/00 ,  G11C11/02 ,  H01F10/32 ,  H01F41/30 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/22 ,  H01L29/76 ,  H01L31/119 ,  H01L43/08 ,  H01L43/12

CPC classification number: C23F4/00 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F41/308 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A method of manufacturing a magnetic memory device includes forming an insulation layer on a substrate, forming a lower electrode on the insulation layer, forming a magneto-resistive film on an upper surface of the lower electrode, the magneto-resistive film including an insulation barrier layer and a plurality of magnetic films stacked on both sides of the insulation barrier layer, stacking a mask layer on the magneto-resistive film, performing ion etching on the magneto-resistive film, using the mask layer as a mask, thereby forming a magneto-resistive element, forming an insulation film on upper surfaces of the mask, the magneto-resistive element and the lower electrode, and etching the insulation film with an ion beam such that a side surface of the magneto-resistive element is exposed.

Abstract translation: 一种制造磁存储器件的方法包括在衬底上形成绝缘层，在绝缘层上形成下电极，在下电极的上表面上形成磁阻膜，该磁阻膜包括绝缘屏障 层和层叠在绝缘阻挡层的两侧的多个磁性膜，使用掩模层作为掩模将掩模层堆叠在磁阻膜上，对磁阻膜进行离子蚀刻，从而形成磁 电阻元件，在掩模的上表面，磁阻元件和下电极上形成绝缘膜，并用离子束蚀刻绝缘膜，使得磁阻元件的侧表面露出。

公开(公告)号：US20050248980A1

公开(公告)日：2005-11-10

申请号：US11179252

申请日：2005-07-12

Applicant: Cherng-Chyi Han ,  Liubo Hong

Inventor： Cherng-Chyi Han ,  Liubo Hong

IPC: H01F10/32 ,  G11C11/14 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L29/82 ,  H01L31/062 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: A method for forming MRAM cell structures wherein the topography of the cell is substantially flat and the distance between a bit line and a magnetic free layer, a word line and a magnetic free layer or a word line and a bit line and a magnetic free layer is precise and well controlled. The method includes the formation of an MTJ film stack over which is formed both a capping and sacrificial layer. The stack is patterned by conventional means, then is covered by a layer of insulation which is thinned by CMP to expose a remaining portion of the sacrificial layer. The remaining portion of the sacrificial layer can be precisely removed by an etching process, leaving only the well dimensioned capping layer to separate the bit line from the magnetic free layer and the capping layer. The bit line and an intervening layer of insulation separate the free layer from a word line in an equally precise and controlled manner.

Abstract translation: 一种用于形成MRAM单元结构的方法，其中单元的形貌基本上是平坦的，并且位线和无磁性层，字线和无磁性层或字线以及位线和无磁层之间的距离 是精确和良好的控制。 该方法包括形成MTJ膜堆叠，在其上形成封盖层和牺牲层。 堆叠通过常规方式图案化，然后被由CMP稀疏以暴露牺牲层的剩余部分的绝缘层覆盖。 可以通过蚀刻工艺精确地去除牺牲层的剩余部分，仅留下孔尺寸的覆盖层以将位线与无磁性层和封盖层分离。 位线和绝缘层的绝缘层以同样精确和受控的方式将自由层与字线分开。

公开(公告)号：US20050247987A1

公开(公告)日：2005-11-10

申请号：US11121495

申请日：2005-05-03

Applicant: Sang Lee

Inventor： Sang Lee

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

Abstract: A flash memory device and a method for fabricating the same is disclosed that reduces or prevents mis-operation and improves integration, which includes a semiconductor substrate having a field region and an active region; a device isolation layer on the field region including a conductive (e.g., polysilicon) layer and an insulating layer thereon; a sidewall spacer at sides of the device isolation layer; an ONO layer on the active region; a gate electrode on the ONO layer; source and drain regions at sides of the gate electrode in the active region; a passivation layer on the semiconductor substrate, having a contact hole in the drain region; and a drain electrode in the contact hole, connected with the drain region.

Abstract translation: 公开了一种闪存器件及其制造方法，其减少或防止错误操作和改进集成，其包括具有场区域和有源区域的半导体衬底; 在场区域上的器件隔离层，包括导电（例如多晶硅）层和绝缘层; 在所述器件隔离层的侧面处的侧壁间隔物; 活性区上的ONO层; ONO层上的栅电极; 源极和漏极区域在栅电极的有源区中; 半导体衬底上的钝化层，在漏区中具有接触孔; 和接触孔中的漏电极，与漏区连接。

公开(公告)号：US06963513B2

公开(公告)日：2005-11-08

申请号：US10919350

申请日：2004-08-17

Applicant: Toshitaka Yamamoto ,  Shouji Satou

Inventor： Toshitaka Yamamoto ,  Shouji Satou

IPC: H01L27/10 ,  G06F13/28 ,  G11C11/00 ,  G11C16/22 ,  G11C17/10 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/112

CPC classification number: H01L27/11206 ,  G11C16/22 ,  G11C17/10 ,  G11C2216/26 ,  H01L27/112 ,  H01L27/11226 ,  H01L27/11521

Abstract: The present invention provides a technology capable of shortening a TAT of a microcomputer with a nonvolatile memory built therein and achieving a reduction in cost. Flash ROMs comprising memory cells each substantially identical in structure to each of memory cells of a flash memory are formed in their corresponding chips lying in a wafer. Subsequently, memory information is written into each of the memory cells of the flash ROM in a probe test process. Thereafter, the memory information written into the memory cell thereof is made unreprogrammable to thereby disable rewriting of the post-shipment memory information. Thus, the shortening of a TAT can be achieved as compared with a mask ROM built-in microcomputer, and management and fabrication costs can be reduced.

Abstract translation: 本发明提供一种能够缩短微型计算机的TAT的技术，其中内置非易失性存储器并实现成本的降低。 在其相应的位于晶片中的芯片中形成包括与闪速存储器的每个存储单元的结构基本相同的存储单元的闪存ROM。 随后，在探针测试过程中将存储器信息写入闪存ROM的每个存储器单元。 此后，写入其存储单元的存储器信息不可编程，从而禁止重新写入出货后存储器信息。 因此，与掩模ROM内置的微型计算机相比，可以实现TAT的缩短，并且可以降低管理和制造成本。

公开(公告)号：US06963100B2

公开(公告)日：2005-11-08

申请号：US10232703

申请日：2002-09-03

Applicant: Shigeru Kusunoki

Inventor： Shigeru Kusunoki

IPC: H01L21/8247 ,  H01L21/74 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L29/4983 ,  H01L21/743 ,  H01L29/42368 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4966 ,  H01L29/78612

Abstract: Performance for a gate insulation film of an insulated gate transistor is enhanced. A depletion layer is generated in a region of a gate electrode 12 which is provided in contact with a gate insulation film 4 in an OFF state, and the depletion layer disappears or a width thereof is reduced in an ON state.

Abstract translation: 提高了绝缘栅极晶体管的栅极绝缘膜的性能。 在栅极电极12的区域中产生耗尽层，栅极电极12设置为与栅极绝缘膜4接触处于断开状态，并且耗尽层消失或其宽度在导通状态下降低。

公开(公告)号：US06963099B2

公开(公告)日：2005-11-08

申请号：US10915511

申请日：2004-08-10

Applicant: Yoshiaki Fukuzumi

Inventor： Yoshiaki Fukuzumi

IPC: H01L27/105 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  H01L29/76

CPC classification number: H01L27/228 ,  B82Y10/00 ,  H01L43/08

Abstract: A magnetic memory device includes a magnetoresistance configured to store information. A first wiring is provided along a first direction. The first wiring has a function of applying a magnetic field to the magnetoresistance element. The first wiring has a first surface and a second surface. The second surface faces the magnetoresistance element and the first surface is opposite to it. The second surface is smaller in width than the first surface.

公开(公告)号：US06963097B2

公开(公告)日：2005-11-08

申请号：US10730855

申请日：2003-12-08

Applicant: Soon-Yong Kweon

Inventor： Soon-Yong Kweon

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L28/57 ,  H01L21/76895 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/75

Abstract: The method for manufacturing an FeRAM capacitor with a merged top electrode plate line (MTP) structure is employed to prevent a detrimental impact on the FeRAM and to secure a reliable FeRAM device. The method includes steps of: preparing an active matrix obtained by a predetermined process; forming a first conductive layer, a dielectric layer and a second conductive layer on the active matrix in sequence; forming a hard mask on the second conductive layer; patterning the second conductive layer, the dielectric layer and the first conductive layer by using the hard mask, thereby forming a vertical capacitor stack, a width of the capacitor stack being larger than that of the storage node contact; forming a second ILD embracing the capacitor stack; planarizing the second ILD till the top face of the hard mask is exposed; removing the hard mask to form an opening above the top electrode; and forming a plate line of which a width is larger than that of the capacitor stack.

Abstract translation: 采用具有合并的顶电极板线（MTP）结构的FeRAM电容器的制造方法来防止对FeRAM的不利影响并确保可靠的FeRAM器件。 该方法包括以下步骤：制备通过预定方法获得的有源矩阵; 在有源矩阵上依次形成第一导电层，电介质层和第二导电层; 在所述第二导电层上形成硬掩模; 通过使用硬掩模图案化第二导电层，电介质层和第一导电层，从而形成垂直电容器堆叠，电容器堆叠的宽度大于存储节点接触的宽度; 形成包围电容器堆叠的第二ILD; 将第二ILD平坦化直到硬掩模的顶面露出; 去除硬掩模以在顶部电极上方形成开口; 并且形成宽度大于电容器叠层宽度的板线。

公开(公告)号：US06960815B2

公开(公告)日：2005-11-01

申请号：US10379656

申请日：2003-03-06

Applicant: Hiroaki Yoda ,  Yoshiaki Asao ,  Tomomasa Ueda ,  Minoru Amano ,  Tatsuya Kishi ,  Keiji Hosotani ,  Junichi Miyamoto

Inventor： Hiroaki Yoda ,  Yoshiaki Asao ,  Tomomasa Ueda ,  Minoru Amano ,  Tatsuya Kishi ,  Keiji Hosotani ,  Junichi Miyamoto

IPC: G11C11/15 ,  G11C11/00 ,  G11C11/16 ,  H01L21/00 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/105 ,  H01L27/22 ,  H01L29/82 ,  H01L43/00 ,  H01L43/08

CPC classification number: G11C11/16 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/08

Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.

Abstract translation: 磁存储装置包括沿第一方向延伸的第一布线，沿第二方向延伸的第二布线，布置在第一布线和第二布线之间的交叉点处的磁阻元件，至少覆盖第一布线 第一绕线的下表面和两个侧表面中的任一个，覆盖第二布线的上表面和两个侧表面中的至少一个的第二轭主体，布置在第二布线的两侧上的第一和第二轭尖 磁阻元件以与磁阻元件间隔的方式在第一方向上，以及第三和第四磁轭尖端，其在与磁阻元件间隔开的第二方向上布置在磁阻元件的两侧。

公开(公告)号：US20050237794A1

公开(公告)日：2005-10-27

申请号：US11167411

申请日：2005-06-28

Applicant: Hideto Hidaka

Inventor： Hideto Hidaka

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C29/12 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  G11C11/44

CPC classification number: H01L27/228 ,  G11C7/14 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/224

Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

公开(公告)号：US20050237791A1

公开(公告)日：2005-10-27

申请号：US11108699

申请日：2005-04-19

Applicant: Makoto Motoyoshi

Inventor： Makoto Motoyoshi

IPC: G11C11/15 ,  G11C5/02 ,  G11C11/00 ,  G11C11/16 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C5/025 ,  G11C11/15 ,  G11C11/16

Abstract: A high-capacity magnetic memory device in which the magnetic field for writing is nearly uniform for all memory elements. It is realized by reducing the deformation of resist pattern which occurs in photolithography when mask patterns are close to each other. The magnetic memory device is an MRAM composed of a large number of memory cells, each including one TMR element, one transistor for reading (selection), and reading plugs that connect the TMR element to the transistor for reading (selection). These memory cells are arranged such that the TMR elements are in a pattern of translational symmetry. For writing, memory cells are connected by the bit lines and the writing word lines which intersect orthogonally. The long axis of the TMR element is oriented aslant 45° with respect to these lines, so that the TMR elements are capable of toggle-mode writing.

Abstract translation: 一种大容量磁存储器件，其中用于写入的磁场对于所有存储元件几乎是均匀的。 通过减小当掩模图案彼此接近时在光刻中发生的抗蚀剂图案的变形来实现。 磁存储器件是由大量存储器单元构成的MRAM，每个存储单元包括一个TMR元件，一个用于读取（选择）的晶体管，以及读取将TMR元件连接到晶体管用于读取（选择）的插头。 这些存储单元被布置成使得TMR元件处于平移对称的图案。 对于写入，存储单元通过位线和与正交相交的写入字线连接。 TMR元件的长轴相对于这些线取向倾斜45°，使得TMR元件能够进行触发模式写入。