公开(公告)号：US20240257885A1

公开(公告)日：2024-08-01

申请号：US18618460

申请日：2024-03-27

Applicant: SK hynix Inc.

Inventor： Yeong Jo MUN ,  Sung Hyun HWANG

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/0483

Abstract: A memory device may include: a control circuit suitable for performing a program loop including a program operation including a program voltage application operation on a selected word line and a bit line setup operation on a plurality of bit lines and a verification operation of applying (N−1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic suitable for controlling the control circuit to repeatedly perform the program loop until programming for the selected word line is completed, and controlling the control circuit to apply any one of N types of column voltages to each of the plurality of bit lines in the bit line setup operation included in a second program loop.

公开(公告)号：US12051469B2

公开(公告)日：2024-07-30

申请号：US17825960

申请日：2022-05-26

Applicant: Intel NDTM US LLC

Inventor： Wei Cao ,  Richard M. Fastow ,  Xuehong Yu ,  Xin Sun ,  Hyungseok Kim ,  Narayanan Ramanan ,  Amol R. Joshi ,  Krishna Parat

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

公开(公告)号：US12046306B2

公开(公告)日：2024-07-23

申请号：US17826434

申请日：2022-05-27

Applicant: SanDisk Technologies LLC

Inventor： Sujjatul Islam ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26

Abstract: The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a maximum number of program loops. The maximum number of program loops is dependent on the temperature that is detected.

公开(公告)号：US12046299B2

公开(公告)日：2024-07-23

申请号：US18176597

申请日：2023-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Amit Berman ,  Evgeny Blaichman ,  Ron Golan ,  Sergey Gendel

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G11C16/04 ,  G11C16/26 ,  G06N20/00 ,  G11C16/08

CPC classification number: G11C16/26 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/0483 ,  G06N20/00 ,  G11C16/08

Abstract: Systems and methods of the present disclosure may be used to improve equalization module architectures for NAND cell read information. For example, embodiments of the present disclosure may provide for de-noising of NAND cell read information using a Multiple Shallow Threshold-Expert Machine Learning Models (MTM) equalizer. An MTM equalizer may include multiple shallow machine learning models, where each machine learning model is trained to specifically solve a classification task (e.g., a binary classification task) corresponding to a weak decision range between two possible read information values for a given NAND cell read operation. Accordingly, during inference, each read sample with a read value within a weak decision range is passed through a corresponding shallow machine learning model (e.g., a corresponding threshold expert) that is associated with (e.g., trained for) the particular weak decision range.

公开(公告)号：US12046287B2

公开(公告)日：2024-07-23

申请号：US18173730

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Joe ,  Kang-Bin Lee

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

公开(公告)号：US20240242769A1

公开(公告)日：2024-07-18

申请号：US18621114

申请日：2024-03-29

Applicant: Kioxia Corporation

Inventor： Hideyuki KATAOKA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell; a word line coupled to a gate of the first memory cell; a first transistor having a first end coupled to the word line; and a control circuit configured to, in a read operation, apply a first voltage, which is positive, to a back gate of the first transistor.

公开(公告)号：US20240233825A9

公开(公告)日：2024-07-11

申请号：US18489454

申请日：2023-10-18

Applicant: Micron Technology, Inc.

Inventor： Federica Paolini ,  Violante Moschiano ,  Marco Domenico Tiburzi ,  Leo Raimondo ,  Filippo Bruno ,  Shigekazu Yamada

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30

Abstract: A system includes a memory device having one or more planes and a first set of voltage regulators coupled to each plane of the one or more planes, where the first set of voltage regulators is shared by the one or more planes. The system includes a second set of voltage regulators coupled to a plane of the one or more planes configured to supply a respective voltage to one or more conductive lines responsive to a memory access operation request. The system includes a switch, at the plane of the one or more planes, coupled with a first voltage regulator of the first set of voltage regulators, a second voltage regulator of the second set of voltage regulators, and a first conductive line, the switch configured to selectively couple the second voltage regulator of the second set of voltage regulators to the first conductive line.

公开(公告)号：US12033707B2

公开(公告)日：2024-07-09

申请号：US18301377

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Min Kang ,  Dongku Kang ,  Su Chang Jeon ,  Won-Taeck Jung

IPC: G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/3481 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30

Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device incudes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.

公开(公告)号：US12033704B2

公开(公告)日：2024-07-09

申请号：US17952659

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Junya Matsuno ,  Kenro Kubota ,  Masato Dome ,  Kensuke Yamamoto ,  Kei Shiraishi ,  Kazuhiko Satou ,  Ryo Fukuda ,  Masaru Koyanagi

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.

公开(公告)号：US12029031B2

公开(公告)日：2024-07-02

申请号：US18314527

申请日：2023-05-09

Applicant: KIOXIA CORPORATION

Inventor： Takehiko Amaki ,  Yoshihisa Kojima ,  Toshikatsu Hida ,  Marie Grace Izabelle Angeles Sia ,  Riki Suzuki ,  Shohei Asami

IPC: H10B41/27 ,  G11C7/04 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.