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公开(公告)号：US12099728B2
公开(公告)日：2024-09-24
申请号：US17955018
申请日：2022-09-28
Applicant: SanDisk Technologies LLC
Inventor： Towhidur Razzak , Ravi Kumar , Abu Naser Zainuddin , Jiahui Yuan
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/0629 , G06F3/0679
Abstract: In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be lower. To address the word line dependency, the dummy memory cells connected to the dummy word line can be programmed to different threshold voltages based on which data word line is to be programmed. Thus, prior to programming data non-volatile memory cells connected to a particular data word line, the dummy memory cells are programmed to a threshold voltage that is chosen based on the position of the particular data word line.
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公开(公告)号：US20220165342A1
公开(公告)日：2022-05-26
申请号：US17102657
申请日：2020-11-24
Applicant: SanDisk Technologies LLC
Inventor： Xue Bai Pitner , Deepanshu Dutta , Ravi Kumar
Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses.
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公开(公告)号：US20210327520A1
公开(公告)日：2021-10-21
申请号：US16854030
申请日：2020-04-21
Applicant: SanDisk Technologies LLC
Inventor： Xue Pitner , Deepanshu Dutta , Huai-Yuan Tseng , Ravi Kumar , Cynthia Hsu
Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.
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4.发明授权公开(公告)号：US12154625B2
公开(公告)日：2024-11-26
申请号：US17667100
申请日：2022-02-08
Applicant: SanDisk Technologies LLC
Inventor： Sujjatul Islam , Ravi Kumar
Abstract: The memory device includes an array of memory cells, which are configured to retain multiple bits per memory cell, arranged in a plurality of word lines. A controller is configured to program the memory cells of a selected word line in a first programming pass. The first programming pass includes a plurality of programming pulses, each including the application of a programming voltage Vpgm by the controller to a control gate of the selected word line for a first duration. The controller is also configured to further program the memory cells of the selected word line in a second programming pass. The second programming pass includes a plurality of programming pulses, each of which includes the application of a programming voltage Vpgm by the controller to the control gate of the selected word line for a second duration that is different than the first duration.
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公开(公告)号：US20230274785A1
公开(公告)日：2023-08-31
申请号：US17682280
申请日：2022-02-28
Applicant: SanDisk Technologies LLC
Inventor： Sujjatul Islam , Yu-Chung Lien , Ravi Kumar , Xue Pitner
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/24 , G11C16/14 , G11C16/26
Abstract: A non-volatile semiconductor memory device comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.
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Patent Agency Ranking
公开(公告)号：US20230197173A1
公开(公告)日：2023-06-22
申请号：US17554321
申请日：2021-12-17
Applicant: SanDisk Technologies LLC
Inventor： Xue Bai Pitner , Prafful Golani , Ravi Kumar
CPC classification number: G11C16/3459 , G11C16/0483 , G11C16/26
Abstract: A method for performing a program verify operation with respect to a target memory cell in a memory structure of a non-volatile memory system, wherein the method may comprise determining a location of the target memory cell within the structure and, based upon the determined location of the target cell and with respect to each programmable memory state: (1) applying a first sense signal at a first point in time, and (2) applying a second sense signal at a second point in time, wherein a time interval between the first and the second points in time is equal to a predetermined optimal time period plus or minus an offset parameter time value.
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公开(公告)号：US11574693B2
公开(公告)日：2023-02-07
申请号：US17347772
申请日：2021-06-15
Applicant: SanDisk Technologies LLC
Inventor： Chin-Yi Chen , Muhammad Masuduzzaman , Dengtao Zhao , Anubhav Khandelwal , Ravi Kumar
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.
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公开(公告)号：US20220359024A1
公开(公告)日：2022-11-10
申请号：US17307626
申请日：2021-05-04
Applicant: SanDisk Technologies LLC
Inventor： Xue Pitner , Muhammad Masuduzzaman , Ravi Kumar
Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line, during the second pass, a voltage that is applied to at least one memory cell is reduced from a verify voltage by an offset which is determined as a function of a data state of an adjacent memory cell of an adjacent word line and wherein the first pass but not the second pass has been completed in the adjacent word line.
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公开(公告)号：US11361834B1
公开(公告)日：2022-06-14
申请号：US17137871
申请日：2020-12-30
Applicant: SanDisk Technologies LLC
Inventor： Ravi Kumar , Deepanshu Dutta
Abstract: A memory device comprising control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line, that correspond to a first set of data states, are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to cause a first voltage of the selected word line to discharge to a second voltage level corresponding to a second program voltage such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming.
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公开(公告)号：US11342035B1
公开(公告)日：2022-05-24
申请号：US17102657
申请日：2020-11-24
Applicant: SanDisk Technologies LLC
Inventor： Xue Bai Pitner , Deepanshu Dutta , Ravi Kumar
Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses.
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