公开(公告)号：US20230307018A1

公开(公告)日：2023-09-28

申请号：US17897074

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Hideyuki KATAOKA

IPC: G11C7/10 ,  G11C8/08

CPC classification number: G11C7/1069 ,  G11C7/1063 ,  G11C8/08

Abstract: A semiconductor storage device includes a memory string including memory transistors and a control circuit. The control circuit is configured to in response to a first command, perform a first read operation, and in response to a second command received during the first read operation, perform a second read operation. During the first read operation, a voltage of a first selected word line is decreased from a read pass voltage to a first read voltage and then increased to the read pass voltage. During the second read operation, a voltage of a second word line is set to a second read voltage and then increased to the read pass voltage. Voltages of word lines neither selected during the first nor second read operation are maintained between the first and second read operations.

公开(公告)号：US20240242769A1

公开(公告)日：2024-07-18

申请号：US18621114

申请日：2024-03-29

Applicant: Kioxia Corporation

Inventor： Hideyuki KATAOKA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell; a word line coupled to a gate of the first memory cell; a first transistor having a first end coupled to the word line; and a control circuit configured to, in a read operation, apply a first voltage, which is positive, to a back gate of the first transistor.

公开(公告)号：US20240071478A1

公开(公告)日：2024-02-29

申请号：US18504018

申请日：2023-11-07

Applicant: Kioxia Corporation

Inventor： Hideyuki KATAOKA ,  Yoshinao SUZUKI ,  Mai SHIMIZU ,  Kazuyoshi MURAOKA ,  Masami MASUDA ,  Yoshikazu HOSOMURA

IPC: G11C11/4096 ,  G11C5/06 ,  G11C11/4072 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C11/4072 ,  G11C11/4076

Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.

公开(公告)号：US20230083392A1

公开(公告)日：2023-03-16

申请号：US17680144

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu HOSOMURA ,  Hideyuki KATAOKA ,  Yoshinao SUZUKI ,  Mai SHIMIZU ,  Kazuyoshi MURAOKA ,  Masami MASUDA

IPC: H01L27/11524 ,  G11C16/04 ,  G11C5/06 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

Abstract: A semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.

公开(公告)号：US20240379139A1

公开(公告)日：2024-11-14

申请号：US18783345

申请日：2024-07-24

Applicant: Kioxia Corporation

Inventor： Hideyuki KATAOKA

IPC: G11C7/10 ,  G11C8/08

Abstract: A semiconductor storage device includes a memory string including memory transistors and a control circuit. The control circuit is configured to in response to a first command, perform a first read operation, and in response to a second command received during the first read operation, perform a second read operation. During the first read operation, a voltage of a first selected word line is decreased from a read pass voltage to a first read voltage and then increased to the read pass voltage. During the second read operation, a voltage of a second word line is set to a second read voltage and then increased to the read pass voltage. Voltages of word lines neither selected during the first nor second read operation are maintained between the first and second read operations.

公开(公告)号：US20220301630A1

公开(公告)日：2022-09-22

申请号：US17464297

申请日：2021-09-01

Applicant: Kioxia Corporation

Inventor： Takeshi NAKANO ,  Yuzuru SHIBAZAKI ,  Hideyuki KATAOKA ,  Junichi SATO ,  Hiroki DATE

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C29/42

Abstract: A semiconductor storage device in an embodiment includes a plurality of planes each including a memory cell array, a voltage generation circuit configured to apply a first intermediate voltage to an adjacent word line adjacent to a selected word line in a former half of a program period and apply a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period, a discharge circuit configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line, and a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes.

公开(公告)号：US20220270693A1

公开(公告)日：2022-08-25

申请号：US17344000

申请日：2021-06-10

Applicant: Kioxia Corporation

Inventor： Hideyuki KATAOKA

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/04 ,  G11C7/10

Abstract: According to one embodiment, a semiconductor memory device includes: first and second select transistors; first and second select gate lines; first and second interconnects; first and second memory cell transistors; and first and second word lines. In a write operation, after execution of a verify operation, in a period in which the second select transistor is ON, a voltage of the first word line changes from a first voltage to a second voltage and a voltage of the second word line changes from a third voltage applied in the verify operation to a fourth voltage, and after the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, a voltage of the second select gate line changes from a fifth voltage to a sixth voltage.

公开(公告)号：US20210383868A1

公开(公告)日：2021-12-09

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki SHIMIZU ,  Yoshihiko KAMATA ,  Tsukasa KOBAYASHI ,  Hideyuki KATAOKA ,  Koji KATO ,  Takumi FUJIMOTO ,  Yoshinao SUZUKI ,  Yuui SHIMIZU

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.