公开(公告)号：US20240047522A1

公开(公告)日：2024-02-08

申请号：US17880025

申请日：2022-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jhon Jhy LIAW

IPC: H01L29/06 ,  H01L27/118 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L27/11807 ,  H01L27/092 ,  H01L21/823481 ,  H01L29/66545 ,  H01L21/823475 ,  H01L2027/11831 ,  H01L2027/11866

Abstract: A method includes doping a substrate to form a first well region and a second well region having a different conductivity type than the first well region; forming a first fin structure upwardly extending above the first well region and a second fin structure upwardly extending above the second well region; forming a first gate electrode surrounding the first fin structure and a second gate electrode surrounding the second fin structure; forming first source/drain regions adjoining the first fin structure and on opposite sides of the first gate electrode and second source/drain regions adjoining the second fin structure on opposite sides of the second gate electrode; forming an isolation line interposing the first and second gate electrodes and laterally between a first one of the first source/drain regions and a first one of the second source/drain regions.

公开(公告)号：US11894443B2

公开(公告)日：2024-02-06

申请号：US17842718

申请日：2022-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming Zhu ,  Hui-Wen Lin ,  Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/4966

Abstract: A method of making a semiconductor device includes depositing a TiN layer over a substrate. The method further includes doping a first portion of the TiN layer using an oxygen-containing plasma treatment. The method further includes doping a second portion of the TiN layer using a nitrogen-containing plasma treatment, wherein the second portion of the TiN layer directly contacts the first portion of the TiN layer. The method further includes forming a first metal gate electrode over the first portion of the TiN layer. The method further includes forming a second metal gate electrode over the second portion of the TiN layer, wherein the first metal gate electrode has a different work function from the second metal gate electrode, and the second metal gate electrode directly contacts the first metal gate electrode.

公开(公告)号：US20240038593A1

公开(公告)日：2024-02-01

申请号：US18333682

申请日：2023-06-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hao Cai ,  Chia-Hsien Yao ,  Yen-Jun Huang ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/823481 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886

Abstract: A method includes forming first and second fins disposed on a substrate, forming a gate structure over the first and second fins, epitaxially growing a first source/drain (S/D) feature on the first fin and a second S/D feature on the second fin, depositing a dielectric layer covering the first and second S/D features, etching the dielectric layer to form a trench exposing the first and second S/D features, forming a metal structure in the trench and extending from the first S/D feature to the second S/D feature, performing a cut metal process to form an opening dividing the metal structure into a first segment over the first S/D feature and a second segment over the second S/D feature, and depositing an isolation feature in the opening. The isolation feature separates the first segment from the second segment.

公开(公告)号：US20240038592A1

公开(公告)日：2024-02-01

申请号：US18378983

申请日：2023-10-11

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L21/82345 ,  H01L27/1211 ,  H01L21/845 ,  H01L29/7855 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/4966 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/66545

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US11882691B2

公开(公告)日：2024-01-23

申请号：US17858361

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Heon Lee ,  Munjun Kim ,  ByeongJu Bae

IPC: H01L21/3213 ,  H01L21/033 ,  H10B12/00 ,  H01L21/8234

CPC classification number: H10B12/482 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/823475 ,  H01L21/823481 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/485

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

公开(公告)号：US20240021609A1

公开(公告)日：2024-01-18

申请号：US17812744

申请日：2022-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Hemanth Jagannathan ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L29/41741 ,  H01L29/7827 ,  H01L29/66666 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487

Abstract: Embodiments of present invention provide a transistor structure. The transistor structure includes a first vertical fin of a first vertical transistor, the first vertical fin having a first and a second sidewall and a first and a second vertical end; a first bottom source/drain (S/D) region underneath the first vertical fin, wherein the first bottom S/D region having an edge that vertically aligns with the first vertical end of the first vertical fin; and a first gate stack surrounding the first vertical fin, wherein the first bottom S/D region horizontally extends beyond the first vertical fin, except at the edge of the first bottom S/D region that vertically aligns with the first vertical end of the first vertical fin, to have at least a portion vertically underneath the first gate stack. A method of manufacturing the transistor structure is also provided.

公开(公告)号：US11862623B2

公开(公告)日：2024-01-02

申请号：US18167651

申请日：2023-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen Young ,  Chih-Liang Chen ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng ,  Shun-Li Chen ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Chun-Kuang Chen ,  Ru-Gun Liu

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394 ,  H01L23/528 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L27/0207 ,  G06F30/394 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/528 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US20230420455A1

公开(公告)日：2023-12-28

申请号：US17849725

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L29/40 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439 ,  H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481

Abstract: A semiconductor device includes a plurality of stacks that each includes a plurality of nanostructures stacked over each other, a gate structure wrapping around the nanostructures and extending between the stacks, source and drain structures, and a plurality of fin structures respectively disposed on the stacks. A first surface of the gate structure between the stacks is substantially coplanar with first surfaces of the fin structures facing to the nanostructures or between the first surfaces of the fin structures and the nanostructures.

公开(公告)号：US20230411485A1

公开(公告)日：2023-12-21

申请号：US18361705

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Huan-Chieh SU ,  Li-Zhen YU ,  Chun-Yuan CHEN ,  Cheng-Chi CHUANG ,  Shang-Wen CHANG ,  Yi-Hsun CHIU ,  Pei-Yu WANG ,  Ching-Wei TSAI ,  Chih-Hao WANG

IPC: H01L29/45 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/458 ,  H01L21/823418 ,  H01L29/42392 ,  H01L27/088 ,  H01L29/41733 ,  H01L21/823475

Abstract: An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

公开(公告)号：US11837644B2

公开(公告)日：2023-12-05

申请号：US16579069

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami Hourani ,  Richard Vreeland ,  Giselle Elbaz ,  Manish Chandhok ,  Richard E. Schenker ,  Gurpreet Singh ,  Florian Gstrein ,  Nafees Kabir ,  Tristan A. Tronic ,  Eungnak Han

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/7851

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.