公开(公告)号：US11715535B2

公开(公告)日：2023-08-01

申请号：US17181660

申请日：2021-02-22

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu Harada ,  Yuji Nagai ,  Kenro Kikuchi

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C7/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C7/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes a memory cell connected to a word line, and a control circuit configured to execute a write operation that repeats a program loop including a program operation of applying a program voltage to the word line and a verification operation to be executed after the program operation. The control circuit, during the write operation, increases the program voltage by a first amount each time the program loop is repeated, and after the write operation is interrupted and resumed, changes the increase in the program voltage from the first amount to a second amount, which is a positive number smaller than the first amount.

公开(公告)号：US11715527B2

公开(公告)日：2023-08-01

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka Ikegami ,  Hidehiro Shiga ,  Takashi Maeda ,  Rieko Funatsuki ,  Takayuki Miyazaki

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/20 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US11710528B2

公开(公告)日：2023-07-25

申请号：US17487792

申请日：2021-09-28

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Hongmei Wang ,  Mingdong Cui

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.

公开(公告)号：US11710526B2

公开(公告)日：2023-07-25

申请号：US17578244

申请日：2022-01-18

Applicant: KIOXIA CORPORATION

Inventor： Naoki Kimura

IPC: G01R19/165 ,  G11C16/30 ,  H02H3/20 ,  G11C5/14 ,  G06F1/30

CPC classification number: G11C16/30 ,  G01R19/165 ,  G01R19/16533 ,  G06F1/30 ,  G11C5/143 ,  H02H3/20

Abstract: A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.

公开(公告)号：US20230223084A1

公开(公告)日：2023-07-13

申请号：US17571124

申请日：2022-01-07

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Fanqi Wu ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C7/10

CPC classification number: G11C16/102 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C7/1048

Abstract: A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.

公开(公告)号：US20230205690A1

公开(公告)日：2023-06-29

申请号：US17646253

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He ,  Min Rui Ma

IPC: G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04

CPC classification number: G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/0483 ,  G06F2212/1032

Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.

公开(公告)号：US11688474B2

公开(公告)日：2023-06-27

申请号：US17234502

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10 ,  G11C16/04 ,  G11C16/24 ,  G11C7/06 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C7/065 ,  G11C7/1048 ,  G11C16/0433 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3409

Abstract: A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.

公开(公告)号：US11688462B2

公开(公告)日：2023-06-27

申请号：US17353983

申请日：2021-06-22

Applicant: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY) ,  PeDiSem Co., Ltd.

Inventor： Yun Heub Song ,  Chang Eun Song

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Disclosed is a three-dimensional flash memory including a back gate, which includes word lines extended and formed in a horizontal direction on a substrate so as to be sequentially stacked, and strings penetrating the word lines and extended and formed in one direction on the substrate. Each of the strings includes a channel layer extended and formed in the one direction, and a charge storage layer extended and formed in the one direction to surround the channel layer, the channel layer and the charge storage layer constitute memory cells corresponding to the word lines, and the channel layer includes a back gate extended and formed in the one direction, with at least a portion of the back gate surrounded by the channel layer, and an insulating layer extended and formed in one direction between the back gate and the channel layer.

公开(公告)号：US20230197162A1

公开(公告)日：2023-06-22

申请号：US17657814

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Himanshu Saxena

IPC: G11C16/10 ,  G11C16/28 ,  G11C16/24 ,  G11C16/30 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04 ,  G11C17/12

CPC classification number: G11C16/102 ,  G11C16/28 ,  G11C16/24 ,  G11C16/30 ,  G11C16/08 ,  G11C16/32 ,  G11C16/0433 ,  G11C17/12

Abstract: An OTP memory includes a plurality of bitcells, a plurality of bitlines, each bitline coupled to the plurality of bitcells, and a wordline generation circuit coupled to each of the plurality of bitcells. The wordline generation circuit is configured to control a wordline voltage of at least one selected bitcell of the plurality of bitcells to discharge current of at least one bitline coupled to the at least one selected bitcell during a pre-conditioning phase and to perform a read operation of the at least one selected bitcell following the pre-conditioning phase in a same clock cycle.

公开(公告)号：US20230186954A1

公开(公告)日：2023-06-15

申请号：US18109338

申请日：2023-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuchae LEE ,  Kyudong LEE

IPC: G11C5/04 ,  G11C16/10 ,  G11C11/4074 ,  G11C16/30

CPC classification number: G11C5/04 ,  G11C16/10 ,  G11C11/4074 ,  G11C16/30

Abstract: A memory module is provided including a plurality of semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the plurality of semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group of the semiconductor memory devices and the second group of the semiconductor memory devices through a first transmission line and a second transmission line, respectively. The first transmission line and the second transmission line are physically symmetric with respect to an axis intersecting the control device.