公开(公告)号：US11694731B2

公开(公告)日：2023-07-04

申请号：US17864515

申请日：2022-07-14

Applicant: KIOXIA CORPORATION

Inventor： Akio Sugahara ,  Yoshikazu Harada ,  Shoichiro Hashimoto

IPC: G11C5/14 ,  G11C7/10 ,  G11C7/22 ,  G11C5/02

CPC classification number: G11C7/1063 ,  G11C5/025 ,  G11C7/222

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US11423961B2

公开(公告)日：2022-08-23

申请号：US17203455

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Yoshikazu Harada ,  Shoichiro Hashimoto

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/22

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US11715535B2

公开(公告)日：2023-08-01

申请号：US17181660

申请日：2021-02-22

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu Harada ,  Yuji Nagai ,  Kenro Kikuchi

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C7/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C7/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes a memory cell connected to a word line, and a control circuit configured to execute a write operation that repeats a program loop including a program operation of applying a program voltage to the word line and a verification operation to be executed after the program operation. The control circuit, during the write operation, increases the program voltage by a first amount each time the program loop is repeated, and after the write operation is interrupted and resumed, changes the increase in the program voltage from the first amount to a second amount, which is a positive number smaller than the first amount.

公开(公告)号：US12183389B2

公开(公告)日：2024-12-31

申请号：US17806630

申请日：2022-06-13

Applicant: Kioxia Corporation

Inventor： Manabu Sato ,  Yoshikazu Harada ,  Naoya Shimmyo

IPC: G11C16/08 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/32

Abstract: A semiconductor storage device of an embodiment includes: a plurality of memory strings each including a plurality of memory cell transistors, the plurality of memory strings being connected in parallel to one another; and a control circuit configured to control a write operation on at least part of the plurality of memory cell transistors. The write operation is executed in response to reception of the write command and the address. The control circuit determines, based on the address, whether to perform a first voltage application operation before the write operation ends. The first voltage application operation applies a predetermined voltage to the plurality of word lines.

公开(公告)号：US12086465B2

公开(公告)日：2024-09-10

申请号：US17952402

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Yoshikazu Harada

IPC: G11C16/32 ,  G06F3/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G11C16/10 ,  G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30

Abstract: A semiconductor memory device includes a memory cell array and a control circuit configured to receive a first command set, reject a second command set related to a write operation or an erase operation, in a first time period of executing a first operation on the memory cell array in response to the first command set, receive a third command set related to a read operation in the first time period, and execute the read operation on the memory cell array in response to the third command set.

公开(公告)号：US12033702B2

公开(公告)日：2024-07-09

申请号：US17681662

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu Harada

IPC: G11C16/26

CPC classification number: G11C16/26

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, a word line connected to a gate of each of the memory cell transistors, a sequencer configured to control an operation of the memory cell array, and an input/output circuit. When the input/output circuit receives a command instructing an operation of continuously reading data of a plurality of pages from the memory cell transistors, the sequencer determines the data of the plurality of pages by continuously applying read voltages corresponding to the plurality of pages to be read, to the word line. In each continuous time period during which the control circuit applies read voltages for determining the data of one of the pages to the word line, the control circuit does not apply any read voltage for determining the data of another one of the pages to the word line.

公开(公告)号：US11961583B2

公开(公告)日：2024-04-16

申请号：US18316277

申请日：2023-05-12

Applicant: KIOXIA CORPORATION

Inventor： Akio Sugahara ,  Yoshikazu Harada ,  Shoichiro Hashimoto

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1063 ,  G11C5/025 ,  G11C7/222

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US11348648B2

公开(公告)日：2022-05-31

申请号：US16804019

申请日：2020-02-28

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu Harada

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/14 ,  G11C16/04

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The control circuit is configured to suspend a first operation on the memory cell array while the first operation is being performed, to start a first read operation on the memory cell array, and to resume the suspended first operation at least after the first read operation has been started. Upon receipt of a first command, a setting as to whether or not to resume the suspended first operation in response to receipt of a second command is switched. The second command is different from the first command.

公开(公告)号：US11183256B2

公开(公告)日：2021-11-23

申请号：US16914733

申请日：2020-06-29

Applicant: Kioxia Corporation

Inventor： Koichi Shinohara ,  Katsuki Matsudera ,  Ian Christopher Gamara ,  Yoshikazu Harada ,  Noritaka Kai ,  Yusuke Tanefusa

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  G06F9/30 ,  G11C16/24

Abstract: According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.

公开(公告)号：US11101008B2

公开(公告)日：2021-08-24

申请号：US16806684

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Masato Endo ,  Daisuke Arizono ,  Yoshikazu Harada

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/04 ,  G11C16/12 ,  G11C16/14

Abstract: A semiconductor memory device includes a memory transistor, a word line, a peripheral circuit, and electrodes connected to the peripheral circuit. In response to a write command via the electrodes, the peripheral circuit can execute a first program operation of applying a first program voltage to the word line one time when the write command is one of an n1-th write command to an n2-th write command corresponding to the memory transistor; and execute a second program operation of applying a second program voltage to the first word line at least one time when the write command is one of an (n2+1)-th write command to an n3-th write command corresponding to the memory transistor. The second program voltage in a k-th second program operation is less than the first program voltage in a k-th first program operation.