公开(公告)号：US12159040B2

公开(公告)日：2024-12-03

申请号：US17899974

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Sumiko Domae ,  Kazutaka Ikegami

IPC: G06F3/06

Abstract: A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.

公开(公告)号：US12211567B2

公开(公告)日：2025-01-28

申请号：US17816836

申请日：2022-08-02

Applicant: Kioxia Corporation

Inventor： Kazutaka Ikegami ,  Takashi Maeda ,  Reiko Sumi

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.

公开(公告)号：US11901011B2

公开(公告)日：2024-02-13

申请号：US17399548

申请日：2021-08-11

Applicant: Kioxia Corporation

Inventor： Kazutaka Ikegami ,  Hidehiro Shiga

IPC: G11C16/04 ,  G11C16/10 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor storage device includes a first word line, a second word line provided in the same layer with the first word line and configured to be controlled independently from the first word line, a plurality of memory pillars between the first word line and the second word line, each of the plurality of memory pillars including a first memory cell facing to the first word line and a second memory cell facing to the second word line, the plurality of memory pillars being arranged in a first direction and a second direction intersecting to the first direction and a control circuit. The control circuit is configured to perform a write operation to the second memory cell included in the plurality of memory pillars after performing a write operation to the first memory cell included in each of the plurality of memory pillars.

公开(公告)号：US11715527B2

公开(公告)日：2023-08-01

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka Ikegami ,  Hidehiro Shiga ,  Takashi Maeda ,  Rieko Funatsuki ,  Takayuki Miyazaki

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/20 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US12211557B2

公开(公告)日：2025-01-28

申请号：US18176507

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Kyosuke Sano ,  Kazutaka Ikegami ,  Takashi Maeda

IPC: G11C16/14 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  H10B41/35 ,  H10B41/41

Abstract: A semiconductor memory device includes a first memory pillar and a sequencer. The first memory pillar is sandwiched between a first word line and a second word line, sandwiched between a third word line and a fourth word line, sandwiched between a fifth word line and a sixth word line, includes a first memory cell facing the first word line, a second memory cell facing the second word line, a third memory cell facing the third word line, a fourth memory cell facing the fourth word line, a fifth memory cell facing the fifth word line and a sixth memory cell facing the sixth word line. The sequencer executes an erase operation on the first to sixth memory cells to enable execution of a primary write operation for the first memory cell and a primary write operation for the second memory cell at different timings.

公开(公告)号：US12165708B2

公开(公告)日：2024-12-10

申请号：US18068605

申请日：2022-12-20

Applicant: KIOXIA CORPORATION

Inventor： Reiko Sumi ,  Kazutaka Ikegami

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/34

Abstract: A semiconductor memory device comprises: a semiconductor layer extending in a first direction; a first and second conductive layer facing the semiconductor layer from one side and the other side in a second direction; and a charge storage layer comprising portions provided between the semiconductor layer and first conductive layer and between the semiconductor layer and second conductive layer. The semiconductor memory device is configured to execute erase operation, first write operation, and second write operation. In the first write operation, the first and second conductive layers are applied with first program voltage. In the second write operation, the first conductive layer is applied with second program voltage, and second conductive layer is applied with second voltage lower than the second program voltage. The second write operation is executed after execution of the erase operation and before execution of the first write operation.

公开(公告)号：US11769554B2

公开(公告)日：2023-09-26

申请号：US17447464

申请日：2021-09-13

Applicant: Kioxia Corporation

Inventor： Kyosuke Sano ,  Kazutaka Ikegami ,  Takashi Maeda ,  Rieko Funatsuki

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/30 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.