公开(公告)号：US09425296B2

公开(公告)日：2016-08-23

申请号：US14021795

申请日：2013-09-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Ming Cai ,  Bin Yang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/66977 ,  H01L29/66356 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7827

Abstract: A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall.

Abstract translation: 隧道场晶体管（TFET）器件包括从衬底表面突出的鳍结构。 翅片结构包括靠近基底表面的基部，顶部和从基部延伸到顶部的第一对侧壁。 第一对侧壁的长度对应于翅片结构的长度。 翅片结构还包括在鳍结构的基部处具有第一掺杂剂浓度的第一掺杂区域。 鳍结构还包括在鳍结构的顶部具有第二掺杂剂浓度的第二掺杂区。 TFET器件还包括栅极，其包括与第一对侧壁的第一侧壁相邻的第一导电结构。 电介质层将第一导电结构与第一侧壁电隔离。

公开(公告)号：US09406689B2

公开(公告)日：2016-08-02

申请号：US14044725

申请日：2013-10-02

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Seung Hyuk Kang

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7883 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film.

Abstract translation: 一种制造多时间可编程（MTP）器件的方法包括在第二导电类型的衬底上形成第一导电类型的鳍片。 该方法还包括形成浮动栅极电介质以部分地围绕鳍片。 该方法还包括在浮栅电介质上形成浮栅。 该方法还包括在浮栅上形成耦合膜并在耦合膜上形成耦合栅极。

公开(公告)号：US09263522B2

公开(公告)日：2016-02-16

申请号：US14100760

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/15 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L21/74 ,  H01L29/78

CPC classification number: H01L29/1045 ,  H01L21/743 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: An apparatus comprises a substrate. The apparatus also comprises a diffusion barrier formed on a surface of a first region of the substrate. The diffusion barrier is formed using a first material having a first band gap energy. The apparatus further comprises a channel region formed on a surface of the diffusion barrier. The channel region is formed using a second material having a second band gap energy that is lower than the first band gap energy. The apparatus further comprises a back gate contact coupled to the first region of the substrate.

Abstract translation: 一种装置包括基板。 该装置还包括形成在基板的第一区域的表面上的扩散阻挡层。 使用具有第一带隙能量的第一材料形成扩散阻挡层。 该装置还包括形成在扩散阻挡层的表面上的沟道区。 沟道区域使用具有低于第一带隙能量的第二带隙能量的第二材料形成。 该装置还包括耦合到衬底的第一区域的背栅极接触。

公开(公告)号：US09245971B2

公开(公告)日：2016-01-26

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  P R Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/8238

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间。

公开(公告)号：US09153587B2

公开(公告)日：2015-10-06

申请号：US14659893

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

IPC: H01L21/336 ,  H01L29/786 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/265 ,  G06F17/50

CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin-type semiconductor device comprises means for providing a first fin-type conduction channel having first and second regions, means for providing a second fin-type conduction channel having a fourth region above a third region, and means for shielding current leakage coupled to at least one of the first region and the third region. The first region has a first doping concentration greater than a second doping concentration of the second region. The first fin-type conduction channel comprises first ion implants implanted into the substrate at a first depth and second ion implants implanted into the substrate at a different depth. The third region has a third doping concentration, and the fourth region has a fourth doping concentration.

Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括用于提供具有第一和第二区域的第一鳍式传导沟道的装置，用于提供具有在第三区域上方的第四区域的第二鳍式传导沟道的装置，以及用于屏蔽漏电耦合到 第一区域和第三区域中的至少一个。 第一区域具有大于第二区域的第二掺杂浓度的第一掺杂浓度。 第一鳍型传导通道包括在第一深度处植入衬底中的第一离子植入物和在不同深度处植入衬底中的第二离子植入物。 第三区域具有第三掺杂浓度，第四区域具有第四掺杂浓度。

公开(公告)号：US20150145592A1

公开(公告)日：2015-05-28

申请号：US14225836

申请日：2014-03-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Daeik Daniel Kim ,  Bin Yang ,  Jonghae Kim ,  Daniel Wayne Perry

IPC: H01L29/739 ,  G05F3/16

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

Abstract translation: 一种方法包括根据场效应晶体管（FET）型操作，偏置第一栅极电压以使单相电流从晶体管的第一区域流过晶体管的第二区域。 该方法还包括偏置主体端子以使得双极电流能够根据双极结型晶体管（BJT）型操作从第一区域流动到第二区域。 单极电流与双极电流同时流动，在互补金属氧化物半导体（CMOS）技术中提供双模数字和模拟器件。

公开(公告)号：US08980708B2

公开(公告)日：2015-03-17

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Bin Yang ,  P R Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L21/8244 ,  H01L23/538 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的至少一部分的第一电容器板和具有至少一部分MIM电容器层的第二电容器板。

公开(公告)号：US12051534B2

公开(公告)日：2024-07-30

申请号：US17226744

申请日：2021-04-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01F27/29 ,  H01F17/00 ,  H01F41/04 ,  H01L49/02

CPC classification number: H01F27/29 ,  H01F17/0013 ,  H01F41/041 ,  H01L28/10 ,  H01F2017/0073

Abstract: Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

公开(公告)号：US20240234418A9

公开(公告)日：2024-07-11

申请号：US18047954

申请日：2022-10-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field effect transistor (VTFET) comprising: a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first plane direction relative to the substrate; and a first p-type FET structure oriented in a second plane direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each comprises a FIN having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height.

公开(公告)号：US20240136357A1

公开(公告)日：2024-04-25

申请号：US18047954

申请日：2022-10-18

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field effect transistor (VTFET) comprising: a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first plane direction relative to the substrate; and a first p-type FET structure oriented in a second plane direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each comprises a FIN having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height.