公开(公告)号：US09818817B2

公开(公告)日：2017-11-14

申请号：US13764811

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  P R Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor reduces the number of masks and processing steps compared to conventional techniques. A conductive redistribution layer (RDL) is patterned on a semiconductor chip. A MIM dielectric layer is deposited over the RDL. A first conductive layer of a MIM capacitor is deposited over the MIM dielectric layer. The MIM dielectric layer is patterned using a MIM conductive layer mask. The conductive redistribution layer includes two RDL nodes that extend under the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

公开(公告)号：US09633996B1

公开(公告)日：2017-04-25

申请号：US15081396

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  P R Chidambaram ,  Haining Yang ,  John Jianhong Zhu ,  Kern Rim

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L49/02 ,  H01L29/94 ,  H01L29/66 ,  H01L27/07

CPC classification number: H01L27/0629 ,  H01L27/0716 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/24 ,  H01L29/0653 ,  H01L29/66181 ,  H01L29/7851 ,  H01L29/94

Abstract: A semiconductor device arranged between a source voltage (Vss) and a power voltage (Vdd) may include a first terminal coupled to the power voltage Vdd. The semiconductor device may also include a decoupling capacitor. The decoupling capacitor may include a semiconductor fin coupled to the first terminal, a dielectric layer on the semiconductor fin, and a gate on the dielectric layer. The semiconductor device may further include a second terminal. The second terminal may include a conductive gate resistor coupled in series with the gate of the decoupling capacitor. The second terminal may be coupled to the source voltage Vss via a first interconnect layer (M1).

公开(公告)号：US09287347B2

公开(公告)日：2016-03-15

申请号：US13765015

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  P R Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L29/49 ,  H01L49/02 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与常规技术相比，金属 - 绝缘体 - 金属（MIM）电容器减少了许多掩模和处理步骤。 MIM电容器的第一导电层沉积在半导体芯片上并使用MIM导电层掩模进行图案化。 导电再分配层（RDL）在MIM介电层上图案化。 导电再分配层包括与MIM电容器的第一导电层重叠的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US09245971B2

公开(公告)日：2016-01-26

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  P R Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/8238

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间。

公开(公告)号：US08980708B2

公开(公告)日：2015-03-17

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Bin Yang ,  P R Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L21/8244 ,  H01L23/538 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的至少一部分的第一电容器板和具有至少一部分MIM电容器层的第二电容器板。