公开(公告)号：US20150076704A1

公开(公告)日：2015-03-19

申请号：US14026893

申请日：2013-09-13

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  John Jianhong Zhu

IPC: H01L23/522 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L21/76816 ,  G06F17/5068 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

Abstract translation: 在特定实施例中，一种方法包括形成与第一侧壁结构相邻并与半导体器件的心轴相邻的第二硬掩模层。 心轴的顶部在形成第二硬掩模层之前被暴露。 该方法还包括去除第一侧壁结构以暴露第一硬掩模层的第一部分。 该方法还包括蚀刻第一硬掩模层的第一部分以暴露电介质材料的第二部分。 该方法还包括蚀刻介电材料的第二部分以形成第一沟槽。 该方法还包括在第一沟槽内形成第一金属结构。

公开(公告)号：US20140138777A1

公开(公告)日：2014-05-22

申请号：US13684087

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Zhongze Wang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit (IC) that includes a metal gate terminal that has a gate metal that is either p-type or n-type. The IC further includes a first semiconductor region having either a p-type doping or an n-type doping, such that if the gate metal is p-type then the first semiconductor region has the n-type doping, and if the gate metal is n-type then the first semiconductor region has the p-type doping. A gate dielectric is interposed between the metal gate terminal and the first semiconductor region. The gate dielectric has a gate breakdown voltage VBDGSD that is reduced in proportion to a built-in electric field EBIGSD associated with a boundary region between the metal gate terminal and the first semiconductor region if a polarity of a programming voltage VPP is oriented parallel to the built-in electric field EBIGSD.

Abstract translation: 一个特征涉及一种集成电路（IC），其包括具有p型或n型栅极金属的金属栅极端子。 IC还包括具有p型掺杂或n型掺杂的第一半导体区域，使得如果栅极金属为p型，则第一半导体区域具有n型掺杂，并且如果栅极金属为 n型，则第一半导体区域具有p型掺杂。 栅极电介质介于金属栅极端子和第一半导体区域之间。 栅极电介质具有栅极击穿电压VBDGSD，其如果编程电压VPP的极性平行于金属栅极端子和第一半导体区域之间的边界区域而与内置电场EBIGSD成比例地减小 内置电场EBIGSD。

公开(公告)号：US20140001568A1

公开(公告)日：2014-01-02

申请号：US13684107

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Zhongze Wang ,  John J. Zhu ,  Xia Li

IPC: H01L27/112 ,  H01L21/8239

CPC classification number: H01L27/11206 ,  G11C17/16 ,  G11C17/165 ,  H01L21/8239 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/1052 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region, and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode, and also includes an antifuse dielectric, and a second conductor. A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor.

Abstract translation: 一个特征涉及一种集成电路，包括存取晶体管和反熔丝。 存取晶体管包括至少一个源极/漏极区域，反熔丝具有导体 - 绝缘体 - 导体结构。 反熔丝包括用作第一电极的第一导体，并且还包括反熔丝电介质和第二导体。 第一电极的第一表面耦合到反熔丝电介质的第一表面，反熔丝电介质的第二表面耦合到第二导体的第一表面。 第二导体电耦合到存取晶体管的源/漏区。 如果在第一电极和第二导体之间施加大于或等于抗熔丝电介质击穿电压的编程电压Vpp，则反熔丝适于从开路状态转换到闭合电路状态。

公开(公告)号：US20240282729A1

公开(公告)日：2024-08-22

申请号：US18171428

申请日：2023-02-20

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Zhongze Wang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H10B80/00

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/02 ,  H01L24/05 ,  H10B80/00 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437

Abstract: A 3D IC package includes a first package die having a first side coupled to a package substrate and a second side coupled to a second package die. The first package die includes vertical interconnects to provide interconnections between the second package die and the package substrate. The vertical interconnects each extend vertically between a first die contact on the first side of the first package die and a second die contact on the second side of the first package die. The second package die couples to the second die contacts of the first package die to form power and/or signal interconnects between the package substrate and the second package die. Horizontal interconnects in a distribution layer on the first side of the first package die distribute power and signals horizontally between the first die contacts and the vertical interconnects.

公开(公告)号：US11790241B2

公开(公告)日：2023-10-17

申请号：US17016130

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Matthias Reisser ,  Saurabh Kedar Pitre ,  Xiaochun Zhu ,  Edward Harrison Teague ,  Zhongze Wang ,  Max Welling

IPC: G06F17/16 ,  G06N3/10 ,  G06N3/047

CPC classification number: G06N3/10 ,  G06F17/16 ,  G06N3/047

Abstract: In one embodiment, a method of simulating an operation of an artificial neural network on a binary neural network processor includes receiving a binary input vector for a layer including a probabilistic binary weight matrix and performing vector-matrix multiplication of the input vector with the probabilistic binary weight matrix, wherein the multiplication results are modified by simulated binary-neural-processing hardware noise, to generate a binary output vector, where the simulation is performed in the forward pass of a training algorithm for a neural network model for the binary-neural-processing hardware.

公开(公告)号：US11626156B2

公开(公告)日：2023-04-11

申请号：US17404378

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang

IPC: G11C7/12 ,  G11C11/413 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419

Abstract: Compute-in-memory (CIM) bit cell array circuits include CIM bit cell circuits for multiply-accumulate operations. The CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form. The CIM bit cell circuits include a true pass-gate circuit and a complement pass-gate circuit for generating a binary product of the weight data and an activation input on a product node. An RWL circuit couples the product node to a ground voltage for initialization. The CIM bit cell circuits also include a plurality of consecutive gates each coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit. Each of the CIM bit cell circuits in the CIM bit cell array circuit is disposed in an orientation of a CIM bit cell circuit layout including the RWL circuit.

公开(公告)号：US11487507B2

公开(公告)日：2022-11-01

申请号：US16868202

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Zhongze Wang ,  Periannan Chidambaram

IPC: G06F7/523 ,  G11C11/412 ,  G11C11/419 ,  G06N3/063

Abstract: A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.

公开(公告)号：US20210343343A1

公开(公告)日：2021-11-04

申请号：US16864005

申请日：2020-04-30

Applicant: QUALCOMM Incorporated

Inventor： Edward Harrison Teague ,  Zhongze Wang ,  Max Welling

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C7/16 ,  G11C7/10

Abstract: In one embodiment, an electronic device includes a compute-in-memory (CIM) array that includes a plurality of columns. Each column includes a plurality of CIM cells connected to a corresponding read bitline, a plurality of offset cells configured to provide a programmable offset value for the column, and an analog-to-digital converter (ADC) having the corresponding bitline as a first input and configured to receive the programmable offset value. Each CIM cell is configured to store a corresponding weight.

公开(公告)号：US10964356B2

公开(公告)日：2021-03-30

申请号：US16706429

申请日：2019-12-06

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Xia Li ,  Ye Lu ,  Yandong Gao

IPC: G11C7/10 ,  G11C7/06 ,  G06N3/06 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4074

Abstract: A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.

公开(公告)号：US10777259B1

公开(公告)日：2020-09-15

申请号：US16415204

申请日：2019-05-17

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Xiaochun Zhu

IPC: G11C11/00 ,  G11C11/412 ,  G06N3/02 ,  H03K19/21 ,  G11C11/418

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for convolution computation. One example apparatus generally includes a static random-access memory (SRAM) having a plurality of memory cells. Each of the plurality of memory cells may include a flip-flop (FF) having an output node and a complementary output node; a first switch coupled between the output node and a bit line (BL) of the SRAM, the first switch having a control input coupled to a word line (WL) of the SRAM; and a second switch coupled between the complementary output node and a complementary bit line (BLB) of the SRAM, the second switch having another control input coupled to a complementary word line (WLB) of the SRAM.