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225 条记录 (耗时 0.051 秒)

    Hybrid interconnect structure for performance improvement and reliability enhancement
    71.
    发明授权
    Hybrid interconnect structure for performance improvement and reliability enhancement 有权
    混合互连结构，用于性能改进和可靠性提升

    公开(公告)号：US07973409B2

    公开(公告)日：2011-07-05

    申请号：US11625576

    申请日：2007-01-22

    申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

    摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

    Complementary field effect transistors having embedded silicon source and drain regions
    72.
    发明授权
    Complementary field effect transistors having embedded silicon source and drain regions 有权
    具有嵌入式硅源极和漏极区域的互补场效应晶体管

    公开(公告)号：US07968910B2

    公开(公告)日：2011-06-28

    申请号：US12103301

    申请日：2008-04-15

    申请人： Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

    IPC分类号： H01L21/02 ,  H01L27/12

    CPC分类号： H01L21/823807 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.

    摘要翻译： 提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。 在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。 第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。 基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。 可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。 基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。 然后可以在嵌入的硅区域中形成源区和漏区。 硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。

    Method of enhancing hole mobility
    73.
    发明授权
    Method of enhancing hole mobility 有权
    增强空穴迁移率的方法

    公开(公告)号：US07863653B2

    公开(公告)日：2011-01-04

    申请号：US11561496

    申请日：2006-11-20

    申请人： Henry K. Utomo ,  Judson R. Holt ,  Haining S. Yang

    发明人： Henry K. Utomo ,  Judson R. Holt ,  Haining S. Yang

    IPC分类号： H01L27/10

    CPC分类号： H01L27/1203 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78687

    摘要： A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silicon layer comprise the same crystalline orientation. The device further includes a graded germanium layer on the first silicon layer, wherein the graded germanium layer contacts a spacer and the first silicon layer and does not contact the oxide layer. A lower portion of the graded germanium layer comprises a higher concentration of germanium than an upper portion of the graded germanium layer, wherein a top surface of the graded germanium layer lacks germanium.

    摘要翻译： 提供一种半导体器件，其包括位于氧化物层之上的第一硅层和第二硅层上的氧化物层，其中氧化物层位于第一硅层和第二硅层之间。 第一硅层和第二硅层包含相同的晶体取向。 所述器件还包括在所述第一硅层上的分级锗层，其中所述分级锗层接触间隔物和所述第一硅层并且不接触所述氧化物层。 分级锗层的下部包含比分级锗层的上部更高浓度的锗，其中分级锗层的顶表面缺少锗。

    Method and apparatus for increase strain effect in a transistor channel
    76.
    发明授权
    Method and apparatus for increase strain effect in a transistor channel 有权
    在晶体管通道中增加应变效应的方法和装置

    公开(公告)号：US07790558B2

    公开(公告)日：2010-09-07

    申请号：US11465663

    申请日：2006-08-18

    申请人： Haining S. Yang ,  Huilong Zhu

    发明人： Haining S. Yang ,  Huilong Zhu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L29/66545 ,  H01L29/7842

    摘要： Method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate. The method utilizes depositing a nitride film along a surface of the substrate and the gate stack. The nitride film is thicker over a surface of the substrate and thinner over a portion of the gate stack.

    摘要翻译： 在具有设置在基板上的栅极堆叠的半导体器件中增强应力的方法。 该方法利用沿着衬底的表面和栅叠层沉积氮化物膜。 氮化物膜在衬底的表面上更厚，并且在栅极堆叠的一部分上更薄。

    Self-aligned and extended inter-well isolation structure
    77.
    发明授权
    Self-aligned and extended inter-well isolation structure 失效
    自对准和扩展的井间隔离结构

    公开(公告)号：US07750429B2

    公开(公告)日：2010-07-06

    申请号：US11748521

    申请日：2007-05-15

    申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

    发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

    IPC分类号： H01L29/78

    CPC分类号： H01L21/76229 ,  H01L21/3086 ,  H01L21/823878

    摘要： A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.

    摘要翻译： 从衬垫层形成基座，使得底座的两个边缘与植入的孔的边界重合。 通过沉积保形介电层在基座上形成延伸基座。 扩展基座的面积暴露在下方的半导体表面凹陷到凹陷深度。 包括至少一个井内隔离沟槽的其它沟槽被光刻图案化。 在反应离子蚀刻之后，形成阱间隔离沟槽和至少一个阱间隔离沟槽。 与现有技术的结构相比，由于较深的底面，间隙隔离沟槽的宽度可能会降低。 在井间隔离结构下面的p阱和n阱之间的边界与井间隔离结构的中间自对准。

    CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE
    79.
    发明申请
    CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE 有权
    载波移动增强信道设备及其制造方法

    公开(公告)号：US20090302412A1

    公开(公告)日：2009-12-10

    申请号：US12132887

    申请日：2008-06-04

    申请人： KANGGUO CHENG ,  Haining S. Yang

    发明人： KANGGUO CHENG ,  Haining S. Yang

    IPC分类号： H01L29/00 ,  H01L21/76 ,  G06F9/45

    CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/7845 ,  Y10S438/926

    摘要： An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

    摘要翻译： 提供了具有应力增强通道的集成电路，设计结构和制造集成电路的方法。 该方法包括在衬底上形成虚拟栅极结构并在虚拟栅极结构中形成沟槽。 该方法还包括用应变诱导材料填充沟槽的一部分并用栅极材料填充沟槽的剩余部分。

    HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING
    80.
    发明申请
    HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING 有权
    高性能3D FET结构及其使用优选结晶蚀刻形成其的方法

    公开(公告)号：US20090267196A1

    公开(公告)日：2009-10-29

    申请号：US12500396

    申请日：2009-07-09

    申请人： Thomas W. Dyer ,  Haining S. Yang

    发明人： Thomas W. Dyer ,  Haining S. Yang

    IPC分类号： H01L29/04

    CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

    摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

    摘要翻译： 本发明涉及高性能三维（3D）场效应晶体管（FET）。 具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。