公开(公告)号：US12245530B2

公开(公告)日：2025-03-04

申请号：US17358223

申请日：2021-06-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Carl Radens ,  Juntao Li ,  Ruilong Xie ,  Praneet Adusumilli ,  Oscar van der Straten ,  Alexander Reznicek

IPC: H10N70/00

Abstract: A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

公开(公告)号：US12219884B2

公开(公告)日：2025-02-04

申请号：US17449515

申请日：2021-09-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Carl Radens ,  Juntao Li ,  Ruilong Xie ,  Praneet Adusumilli ,  Oscar van der Straten ,  Alexander Reznicek ,  Zuoguang Liu ,  Arthur Gasasira

IPC: H10N70/20 ,  H10N70/00

Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

公开(公告)号：US20240421145A1

公开(公告)日：2024-12-19

申请号：US18333953

申请日：2023-06-13

Applicant: International Business Machines Corporation

Inventor： Carl Radens ,  Brent A. Anderson ,  Albert M. Chu ,  Ruilong Xie

IPC: H01L27/02 ,  H10B10/00

Abstract: A semiconductor structure includes a first circuit row including one or more first circuit cells and a second circuit row including one or more second circuit cells. At a cell boundary between the one or more first circuit cells in the first circuit row and the one or more second circuit cells in the second circuit row, one or more first gate regions of the one or more first circuit cells in the first circuit row are staggered with one or more second gate regions of the one or more second circuit cells in the second circuit row.

公开(公告)号：US12113067B2

公开(公告)日：2024-10-08

申请号：US17472759

申请日：2021-09-13

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kangguo Cheng ,  Juntao Li ,  Carl Radens

IPC: H01L21/82 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807

Abstract: An approach provides a semiconductor structure for a first device with a first plurality of channels with a larger horizontal dimension than a vertical dimension of the first plurality of channels a second device comprising a second plurality of channels with a smaller horizontal dimension than the vertical dimension of the second plurality of channels. The first plurality of channels and the second plurality of channels have a same channel width in embodiments of the present invention. The first device is an n-type horizontal gate-all-around device and the second device is a p-type horizontal gate-all-around device.

公开(公告)号：US20240321748A1

公开(公告)日：2024-09-26

申请号：US18188736

申请日：2023-03-23

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Albert M. Chu ,  Geng Han ,  Brent A. Anderson ,  Ruilong Xie ,  Carl Radens ,  Ravikumar Ramachandran ,  Mahender Kumar

IPC: H01L23/528

CPC classification number: H01L23/5286 ,  H01L23/5283

Abstract: A semiconductor structure is presented including a power rail having a non-rectangular shape and a middle-of-line (MOL) contact layer electrically connected to the power rail by a metal wiring layer. The non-rectangular shape of the power rail defines at least one notch. Alternatively, the non-rectangular shape of the power rail defines at least one extension. The power rail can be a via rail or a VARAIL.

公开(公告)号：US20240204042A1

公开(公告)日：2024-06-20

申请号：US18080892

申请日：2022-12-14

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Tao Li ,  Julien Frougier ,  Susan Ng Emans ,  Carl Radens ,  Dureseti Chidambarrao

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/0642 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/785

Abstract: A semiconductor device includes a first gate region and a second gate region. A diffusion break region is between the first gate region and the second gate region. A top surface of the diffusion break region is co-planar with at least one of a top surface of one or more gate contacts and a top surface of one or more source/drain contacts.

公开(公告)号：US11977614B2

公开(公告)日：2024-05-07

申请号：US17479623

申请日：2021-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Carl Radens ,  Lawrence A. Clevenger ,  Daniel James Dechene ,  Hsueh-Chung Chen

IPC: G06F30/00 ,  G06F21/16 ,  G06F30/20 ,  G06F30/30 ,  H05K3/00

CPC classification number: G06F21/16 ,  G06F30/00 ,  G06F30/20 ,  G06F30/30 ,  H05K3/00

Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

公开(公告)号：US20230420371A1

公开(公告)日：2023-12-28

申请号：US17809076

申请日：2022-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Carl Radens ,  Ruilong Xie ,  Albert M. Chu ,  Brent A. Anderson

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11

CPC classification number: H01L23/535 ,  H01L23/5286 ,  H01L27/1104

Abstract: Embodiments are disclosed for a complementary metal oxide semiconductor (CMOS) device. The CMOS device includes a hybrid cross-couple contact. The hybrid cross-couple contact includes a frontside contact to a gate of the CMOS device. The frontside contact is disposed on a frontside of the CMOS device. The hybrid cross-couple contact includes a source contact to a source of the CMOS device. The source contact is disposed on a backside of the CMOS device. The hybrid cross-couple contact includes a drain contact to a drain of the CMOS device. The drain contact is disposed on a backside of the CMOS device.

公开(公告)号：US20230345690A1

公开(公告)日：2023-10-26

申请号：US17660640

申请日：2022-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Carl Radens ,  Junli Wang ,  Ravikumar Ramachandran ,  Julien Frougier ,  Dechao Guo

IPC: H01L27/11 ,  G11C11/412

CPC classification number: H01L27/1104 ,  G11C11/412

Abstract: Embodiments of present invention provide a SRAM device. The SRAM device includes a first, a second, and a third SRAM cell each having a first and a second pass-gate (PG) transistor, wherein the second PG transistor of the second SRAM cell and the first PG transistor of the first SRAM cell are stacked in a first PG transistor cell, and the first PG transistor of the third SRAM cell and the second PG transistor of the first SRAM cell are stacked in a second PG transistor cell. The first and second PG transistors of the first SRAM cell may be stacked on top of, or underneath, the second PG transistor of the second SRAM cell and/or the first PG transistor of the third SRAM cell.

公开(公告)号：US11696518B2

公开(公告)日：2023-07-04

申请号：US16949909

申请日：2020-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Carl Radens ,  Ruilong Xie ,  Juntao Li

IPC: H10N70/20 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  G11C13/0007 ,  H10B63/20 ,  H10N70/063 ,  H10N70/068 ,  H10N70/841 ,  H10N70/8833

Abstract: A non-volatile memory structure, and methods of manufacture, which may include a first memory element and a second memory element between a first terminal and a second terminal. The first memory element and the second memory element may be in parallel with each other between the first and second terminal. This may enable the hybrid non-volatile memory structure to store values as a combination of the conductance for each memory element, thereby enabling better tuning of set and reset conductance parameters.