公开(公告)号：US20210217873A1

公开(公告)日：2021-07-15

申请号：US16742295

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US10998193B1

公开(公告)日：2021-05-04

申请号：US16748898

申请日：2020-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Somnath Ghosh ,  Daniel James Dechene ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3213

Abstract: Integrated chips and methods of forming the same include forming a first set of sidewall spacers on a first mandrel at first vertical level. The first mandrel is etched away. A second set of sidewall spacers is formed on a second mandrel at a second vertical level. A portion of the second set of sidewall spacers vertically overlaps with a portion of the first set of sidewall spacers. The second mandrel is etched away. A first hardmask layer is etched, using the vertically overlapping first set of sidewall spacers and second set of sidewall spacers as a mask.

公开(公告)号：US20220102153A1

公开(公告)日：2022-03-31

申请号：US17546443

申请日：2021-12-09

Applicant: International Business Machines Corporation

Inventor： Stuart Sieg ,  Daniel James Dechene ,  Eric Miller

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

公开(公告)号：US20210265201A1

公开(公告)日：2021-08-26

申请号：US16796079

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Daniel James Dechene ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033

Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

公开(公告)号：US20210210379A1

公开(公告)日：2021-07-08

申请号：US16736478

申请日：2020-01-07

Applicant: International Business Machines Corporation

Inventor： Daniel James Dechene ,  Timothy Mathew Philip ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.

公开(公告)号：US11888048B2

公开(公告)日：2024-01-30

申请号：US17521964

申请日：2021-11-09

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6675 ,  H01L21/0259 ,  H01L21/823431 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/7869

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US11830778B2

公开(公告)日：2023-11-28

申请号：US17095931

申请日：2020-11-12

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Daniel James Dechene ,  Lawrence A. Clevenger ,  Michael Romain ,  Somnath Ghosh

IPC: H01L21/66 ,  H01L23/14 ,  H01L21/67 ,  H01L23/13

CPC classification number: H01L22/20 ,  H01L21/67248 ,  H01L21/67288 ,  H01L23/13 ,  H01L23/14

Abstract: A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.

公开(公告)号：US11211474B2

公开(公告)日：2021-12-28

申请号：US16742295

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US20210296234A1

公开(公告)日：2021-09-23

申请号：US16822803

申请日：2020-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel James Dechene ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Somnath Ghosh ,  Carl Radens

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Power distribution fabrics and methods of forming the same include forming a first layer of parallel conductive lines, having a first width. At least one additional layer of conductive lines is formed over the first layer of conductive lines, with the conductive lines of each successive layer in the at least one additional layer having a different orientation and a different width relative to the conductive lines of the preceding layer.

公开(公告)号：US12080559B2

公开(公告)日：2024-09-03

申请号：US17546443

申请日：2021-12-09

Applicant: International Business Machines Corporation

Inventor： Stuart Sieg ,  Daniel James Dechene ,  Eric Miller

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/66545

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.