公开(公告)号：US09363115B2

公开(公告)日：2016-06-07

申请号：US13539519

申请日：2012-07-02

Applicant: Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Shih-Hung Lan ,  Chih-Hsien Chang

Inventor： Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Shih-Hung Lan ,  Chih-Hsien Chang

IPC: G06F11/07 ,  H04L25/14 ,  G06F13/16

CPC classification number: H04L25/14 ,  G06F13/1689

Abstract: Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.

Abstract translation: 公开了通过调整这些数据位的输入线的定时来对准多个数据位的系统和方法。 实施例包括用于比较多组位的定时的分层结构。 其他实施例包括在3D管芯堆叠架构中对准来自多个芯片的数据位。

公开(公告)号：US09300601B2

公开(公告)日：2016-03-29

申请号：US14682435

申请日：2015-04-09

Applicant: TQ DELTA, LLC

Inventor： Marcos C. Tzannes ,  Edmund Reiter ,  Christopher Cahill

IPC: H04J3/16 ,  H04L12/935 ,  H04L12/54 ,  H04L25/14 ,  H04L12/70

CPC classification number: H04L49/3081 ,  H04L12/5601 ,  H04L25/14 ,  H04L49/60 ,  H04L2012/5615 ,  H04L2012/565 ,  H04L2012/5672 ,  H04L2012/5674

Abstract: A device that includes a plurality of transceivers configurable to simultaneously operate with a combination of bonded and unbonded transceivers. A first transceiver of the plurality of transceivers is operable at a first data rate, and a second transceiver of the plurality of transceivers is simultaneously operable at a second data rate that is different than the first data rate. The first and second transceivers are operable as bonded transceivers and wherein a third transceiver, of the plurality of transceivers, is simultaneously operable at a third data rate and the third transceiver is not bonded with any other transceiver.

公开(公告)号：US09300434B2

公开(公告)日：2016-03-29

申请号：US14125292

申请日：2012-06-08

Applicant: Erik S. Daniel ,  Robert W. Techentin

Inventor： Erik S. Daniel ,  Robert W. Techentin

IPC: H03M13/11 ,  H04L1/00 ,  H04L25/49 ,  H04L25/14 ,  H03M13/51 ,  G06F11/10 ,  G06F13/42

CPC classification number: H04L1/004 ,  G06F11/10 ,  G06F13/423 ,  H03M13/51 ,  H04L1/0042 ,  H04L25/14 ,  H04L25/4908

Abstract: Zero sum signaling schemes utilize coding across data words to allow the use of single-ended buffers while mitigating simultaneous switching noise (SSN) in digital systems. Zero sum signaling may include balanced zero sum coding (target disparity=0) and nearly balanced zero sum coding (target disparity=±d). Zero sum signaling may reduce simultaneous switching noise as compared to single-ended signaling while allowing a reduction in the number of physical channels (e.g. circuit board traces) by nearly a factor of two as compared to differential signaling.

Abstract translation: 零和信令方案利用跨数据字的编码，以允许使用单端缓冲器，同时减轻数字系统中的同时开关噪声（SSN）。 零和信号可以包括平衡零和编码（目标差异= 0）和几乎平衡的零和编码（目标差异=±d）。 与单端信号相比，零和信号可以减少同时的开关噪声，同时允许与差分信号相比将物理信道（例如电路板迹线）的数量减少近一倍。

公开(公告)号：US09287883B2

公开(公告)日：2016-03-15

申请号：US14525957

申请日：2014-10-28

Applicant: FUJITSU LIMITED

Inventor： Takayuki Shibasaki ,  Yukito Tsunoda

IPC: H04L27/06 ,  H03L7/00 ,  H04L7/033 ,  H04L25/14 ,  H04L7/00

CPC classification number: H03L7/00 ,  H03L7/0807 ,  H03L7/081 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033 ,  H04L25/0276 ,  H04L25/14

Abstract: A multi-lane re-timer circuit includes: a clock generation circuit to generate a base clock; and reception circuits to generate a reception clock and receive input data signals from lanes, wherein each of the reception circuits includes: a phase frequency detector to generate phase difference signal and frequency difference signal between the input data signal and the reception clock; a clock data regeneration controller to generate a control signal based on the phase difference signal; a phase rotator to generate the reception clock from the base clock; and a decision circuit to receive the input data signal, and wherein the clock generation circuit includes: an input selector to select a signal; a charge pump to generate a charge signal; a loop filter to remove a high frequency component from the charge signal to output a voltage control signal; and a voltage controlled oscillator to generate the reception clock.

Abstract translation: 多通道重新定时器电路包括：时钟发生电路，用于产生基本时钟; 以及接收电路，用于生成接收时钟并从通道接收输入数据信号，其中每个接收电路包括：相位频率检测器，用于在输入数据信号和接收时钟之间产生相位差信号和频差信号; 时钟数据再生控制器，用于基于所述相位差信号产生控制信号; 从基准时钟产生接收时钟的相位旋转器; 以及判定电路，用于接收所述输入数据信号，并且其中所述时钟产生电路包括：输入选择器，用于选择信号; 电荷泵以产生充电信号; 环路滤波器，用于从所述充电信号中去除高频分量以输出电压控制信号; 以及用于产生接收时钟的压控振荡器。

公开(公告)号：US20150372845A1

公开(公告)日：2015-12-24

申请号：US14767697

申请日：2015-01-06

Applicant: SONY CORPORATION

Inventor： Naoki YOSHIMOCHI ,  Satoshi OKADA ,  Makiko YAMAMOTO

IPC: H04L25/14 ,  H04N21/4385 ,  H04L5/00 ,  H04N21/2389

CPC classification number: H04L25/14 ,  H04L5/0044 ,  H04L5/0091 ,  H04N21/2385 ,  H04N21/2389 ,  H04N21/4381 ,  H04N21/4385 ,  H04N21/6112 ,  H04N21/6118 ,  H04N21/8456

Abstract: The present technology relates to data processing devices and data processing methods that lower costs and enable CB (Channel Bonding). A transmission device divides a BB stream as a stream of BB (Baseband) frames into divisional streams by distributing the BB frames of the BB stream to data slices. The dividing of the BB stream is performed by limiting the data rate ratio between the data rates of the divisional streams. A reception device recomposes the original BB stream from the divisional streams obtained from data transmitted from the transmission device. The present technology can be applied to CB such as PLP (Physical Layer Pipe) bundling.

Abstract translation: 本技术涉及降低成本并实现CB（信道绑定）的数据处理设备和数据处理方法。 发送装置通过将BB流的BB帧分配给数据切片，将BB流作为BB（基带）帧流划分为分割流。 通过限制分割流的数据速率之间的数据速率比来执行BB流的划分。 接收装置根据从发送装置发送的数据获得的分割流重构原始BB流。 本技术可应用于诸如PLP（物理层管道）捆绑的CB。

公开(公告)号：US20150341193A1

公开(公告)日：2015-11-26

申请号：US14816899

申请日：2015-08-03

Applicant: Kandou Labs SA

Inventor： Ali Hormati ,  Amin Shokrollahi ,  Roger Ulrich

IPC: H04L25/03 ,  H04L25/14 ,  H04L25/02

CPC classification number: H04J13/004 ,  H04L25/0272 ,  H04L25/0276 ,  H04L25/03343 ,  H04L25/14 ,  H04L25/4919

Abstract: An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

Abstract translation: 描述了一种有效的通信装置，用于向量信令码，以在集成电路装置之间传输数据和可选的时钟信号。 描述了基于这种称为“ISI比率”的新度量来设计这种装置及其相关代码的方法，其允许更高的通信速度，更低的系统功耗和降低的实现复杂度。

公开(公告)号：US09189012B2

公开(公告)日：2015-11-17

申请号：US13829566

申请日：2013-03-14

Applicant: Jaehyeok Yang ,  Jinho Han ,  Byungkuk Yoon ,  Hyeonmin Bae ,  Jinho Park ,  Taeho Kim

Inventor： Jaehyeok Yang ,  Jinho Han ,  Byungkuk Yoon ,  Hyeonmin Bae ,  Jinho Park ,  Taeho Kim

IPC: G06F1/04 ,  G06F11/00 ,  G06F1/08 ,  H04L25/14 ,  H04L7/00 ,  G06F13/40 ,  G06F13/38 ,  G06F17/30 ,  G06F15/17

CPC classification number: G06F1/08 ,  G06F13/385 ,  G06F13/405 ,  G06F15/17 ,  G06F17/30017 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/093 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0012 ,  H04L7/0025 ,  H04L7/033 ,  H04L7/0337 ,  H04L25/14

Abstract: Disclosed are various exemplary embodiments of a clock recovery apparatus for recovering clock signals of multiple data channels. In one exemplary embodiment a clock recovery apparatus for a plurality of data channels may include a plurality of channel blocks, where each channel block may include a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and a global signal, and a recovery block configured to recover a clock signal for the respective data channel in response to the respective data signal and the global signal. The apparatus may also include a global signal generation block configured to receive and combine the intermediate signals from the plurality of channel blocks to generate the global signal.

Abstract translation: 公开了用于恢复多个数据信道的时钟信号的时钟恢复装置的各种示例性实施例。 在一个示例性实施例中，用于多个数据信道的时钟恢复装置可以包括多个信道块，其中每个信道块可以包括频率检测块，该频率检测块被配置为基于从相应数据信道接收到的相应数据信号来生成中间信号 和全局信号，以及恢复块，被配置为响应于相应的数据信号和全局信号而恢复相应数据信道的时钟信号。 该装置还可以包括全局信号生成块，被配置为接收并组合来自多个信道块的中间信号以产生全局信号。

公开(公告)号：US09100167B2

公开(公告)日：2015-08-04

申请号：US13691482

申请日：2012-11-30

Applicant: Broadcom Corporation

Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J Huang ,  Delong Cui ,  Afshin Momtaz

IPC: G06F1/04 ,  H04L7/033 ,  G06F1/10 ,  H04L25/14 ,  H04L7/00

CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

公开(公告)号：US09071220B2

公开(公告)日：2015-06-30

申请号：US13832990

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H03K17/16 ,  H03H2/00 ,  H04B1/04 ,  H04L25/02 ,  H04L25/14

CPC classification number: H03H2/005 ,  H04B1/04 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/14 ,  Y02D30/30

Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

Abstract translation: 用于差分信号发射机的终端网络电路包括多个n个电阻元件和多个差分信号驱动器。 每个电阻元件的第一端在公共节点处耦合，其中n是整数值，并且是用于发送多个差分信号的导体的数量。 每个差分信号驱动器可以包括正极端子驱动器和负极端子驱动器。 正端子驱动器耦合到第一电阻元件的第二端，而负端子驱动器耦合到第二电阻元件的第二端。 正极端子驱动器和负极端子驱动器分别独立地切换以提供具有幅度和方向的电流。 在传输周期期间，每个电阻元件具有与其它电阻元件不同的幅度和/或方向的电流。

公开(公告)号：US20150180521A1

公开(公告)日：2015-06-25

申请号：US14415914

申请日：2013-07-19

Applicant: The Trustees of Columbia University in the City of New York

Inventor： Karthik Tripurari ,  Peter R. Kinget ,  Harish Krishnaswamy ,  Teng Yang

IPC: H04B1/12 ,  H04L25/14

CPC classification number: H04B1/123 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0086 ,  H04L25/14

Abstract: Circuits and methods for performing harmonic rejection mixing are provided. In some embodiments, the circuit comprises: a first amplifier that amplifies a received signal at a first gain; a second amplifier that amplifies the received signal at a fraction of the first gain; a mixer that receives a local oscillator signal having a first fundamental frequency and the first amplifier output, and outputs a first mixed signal; a second mixer that receives a second local oscillator signal having a fundamental frequency that is a multiple of the first fundamental frequency and the second amplifier output, and outputs a second mixed signal; and an output stage that receives the first and second mixed signals and outputs a sum of the first and second mixed signals.

Abstract translation: 提供用于执行谐波抑制混合的电路和方法。 在一些实施例中，电路包括：第一放大器，其以第一增益放大接收信号; 第二放大器，以第一增益的一小部分放大接收信号; 接收具有第一基频的本地振荡器信号和所述第一放大器输出的混频器，并输出第一混合信号; 接收第二本地振荡器信号的第二混频器，所述第二本机振荡器信号的基频是所述第一基频和所述第二放大器输出的倍数，并输出第二混合信号; 以及输出级，其接收第一和第二混合信号并输出​​第一和第二混合信号的和。