公开(公告)号：US08508006B2

公开(公告)日：2013-08-13

申请号：US13561201

申请日：2012-07-30

Applicant: Guenole Jan ,  Ru-Ying Tong ,  Yu-Jen Wang

Inventor： Guenole Jan ,  Ru-Ying Tong ,  Yu-Jen Wang

IPC: H01L29/82 ,  H01L43/00 ,  H01L29/34 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/30 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/307 ,  H01L29/66007 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract translation: 公开了一种用于自旋电子器件的MTJ，并且包括薄层种子层，其通过（Co / X）n或（CoX）n组合物（其中n为2至30）X覆盖层叠层中的垂直磁各向异性（PMA） 是V，Rh，Ir，Os，Ru，Au，Cr，Mo，Cu，Ti，Re，Mg或Si中的一种，CoX是无序合金。 可以在层压层和隧道势垒层之间形成CoFeB层，以用作（111）层压体和（100）MgO隧道势垒之间的过渡层。 叠层可以用作MTJ中的参考层，偶极子层或自由层。 在300℃和400℃之间的退火可用于进一步增强层压层中的PMA。

公开(公告)号：US08492866B1

公开(公告)日：2013-07-23

申请号：US13345881

申请日：2012-01-09

Applicant: Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  David L. Harmon ,  Richard A. Phelps ,  Yun Shi ,  Michael J. Zierak

Inventor： Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  David L. Harmon ,  Richard A. Phelps ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/861 ,  H01L31/107 ,  H01L29/30 ,  H01L29/866 ,  H01L29/34 ,  H01L29/74 ,  H01L31/111 ,  H01L29/73 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/00 ,  H01L29/864

CPC classification number: H01L29/866 ,  H01L21/76 ,  H01L21/76283 ,  H01L27/0255 ,  H01L29/66106

Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Abstract translation: 公开了一种齐纳二极管，其具有作为阴极接触区域相对于相邻阴极和阳极阱区域之间的界面的位置的函数的可分级反向偏压击穿电压（Vb）。 具体地，阴极和阳极接触区域被定位成与相应的阴极和阳极阱区域相邻，并进一步被隔离区域分离。 然而，当阳极接触区域完全包含在阳极阱区域内时，阴极接触区域的一端横向延伸到阳极阱区域中。 为了选择性地调节二极管的Vb（例如，增加长度减小二极管的Vb，反之亦然），可以预定该端的长度。 还公开了一种集成电路，其结合具有不同反向偏压击穿电压的二极管的多个实例，形成二极管的方法和二极管的设计结构。

公开(公告)号：US20120241912A1

公开(公告)日：2012-09-27

申请号：US13421748

申请日：2012-03-15

Applicant: Takeshi SENDA ,  Koji Araki

Inventor： Takeshi SENDA ,  Koji Araki

IPC: H01L29/34 ,  H01L21/306

CPC classification number: H01L21/306 ,  H01L21/0201 ,  H01L21/3225

Abstract: There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer.

Abstract translation: 提供了硅晶片的热处理方法。 该方法包括以下连续步骤：（a）用氢终止存在于硅晶片的有源表面上的硅原子，其中所述活性表面被镜面抛光，并且半导体器件将形成在所述有源表面上; （b）用氟终止在硅晶片的活性表面上存在的硅原子; （c）在惰性气体气氛或还原气体气氛下将硅晶片快速加热到第一温度，其中第一温度在1300℃至1400℃的范围内; （d）将硅晶片在第一温度下保持一定时间; 和（e）快速冷却硅晶片。

公开(公告)号：US20110117740A1

公开(公告)日：2011-05-19

申请号：US12524246

申请日：2008-01-23

Applicant: Muriel Martinez ,  Corinue Seguin ,  Morgane Logiou

Inventor： Muriel Martinez ,  Corinue Seguin ,  Morgane Logiou

IPC: H01L21/304 ,  H01L29/34 ,  H01L21/306

CPC classification number: H01L21/02024 ,  H01L21/76254

Abstract: A polishing method for a heterostructure of at least one relaxed superficial heteroepitaxial layer on a substrate made of a different material. The method includes a first chemical mechanical polishing step of the surface of the heteroepitaxial layer performed with a polishing cloth having a first compressibility ratio and with a polishing solution having a first silica particle concentration. The first chemical mechanical polishing step is followed by a second chemical mechanical polishing step of the surface of the heteroepitaxial layer, with the second step being performed with a polishing cloth having a second compressibility ratio, higher than the first compressibility ratio, and with a polishing solution having a second silica particle concentration, lower than the first concentration. By this method, improved surface roughness is achieved.

Abstract translation: 在由不同材料制成的基板上的至少一个松弛表面异质外延层的异质结构的抛光方法。 该方法包括用具有第一可压缩比的抛光布和具有第一二氧化硅颗粒浓度的抛光溶液进行的异质外延层的表面的第一化学机械抛光步骤。 第一化学机械抛光步骤之后是异质外延层的表面的第二化学机械抛光步骤，其中第二步骤是用具有高于第一可压缩比的第二压缩率的抛光布和抛光 溶液，其具有低于第一浓度的第二二氧化硅颗粒浓度。 通过这种方法，实现了改进的表面粗糙度。

公开(公告)号：US07856804B2

公开(公告)日：2010-12-28

申请号：US12719999

申请日：2010-03-09

Applicant: Richard I. Laming ,  Mark Begbie ,  Anthony Traynor

Inventor： Richard I. Laming ,  Mark Begbie ,  Anthony Traynor

IPC: H01L29/34

CPC classification number: B81C1/00158 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C99/004 ,  B81C2201/0109 ,  H04R7/10 ,  H04R7/18 ,  H04R19/005 ,  H04R2307/207 ,  Y10S977/733

Abstract: A MEMS device comprising a flexible membrane that is free to move in response to pressure differences generated by sound waves. A first electrode mechanically coupled to the flexible membrane, and together form a first capacitive plate. A second electrode mechanically coupled to a generally rigid structural layer or back-plate, which together form a second capacitive plate. A back-volume is provided below the membrane. A first cavity located directly below the membrane. Interposed between the first and second electrodes is a second cavity. A plurality of bleed holes connected the first cavity and the second cavity. Acoustic holes are arranged in the back-plate so as to allow free movement of air molecules, such that the sound waves can enter the second cavity. The first and second cavities in association with the back-volume allow the membrane to move in response to the sound waves entering via the acoustic holes in the back-plate.

Abstract translation: 包括柔性膜的MEMS器件，其可响应于由声波产生的压力差而自由移动。 机械地耦合到柔性膜的第一电极，并且一起形成第一电容板。 机械耦合到大致刚性的结构层或背板的第二电极，它们一起形成第二电容板。 在膜的下方提供背部体积。 位于膜下方的第一腔。 介于第一和第二电极之间的是第二腔。 多个排放孔连接第一腔和第二腔。 声孔布置在背板中，以便允许空气分子的自由移动，使得声波可以进入第二腔。 与背容积相关联的第一和第二空腔允许膜响应于通过背板中的声孔进入的声波而移动。

公开(公告)号：US20090256241A1

公开(公告)日：2009-10-15

申请号：US12422401

申请日：2009-04-13

Applicant: Kazunari KURITA ,  Shuichi OMOTE

Inventor： Kazunari KURITA ,  Shuichi OMOTE

IPC: H01L29/34 ,  H01L21/304 ,  H01L21/322

CPC classification number: H01L29/34 ,  H01L21/30625 ,  H01L21/3221

Abstract: A method of manufacturing a thin silicon wafer by slicing a silicon single crystal includes: a thinning step S3 of polishing a rear surface of the silicon wafer to reduce the thickness of the silicon wafer after a device structure is formed on a front surface of the silicon wafer; a mirror surface forming step S4 of processing the rear surface of the silicon wafer into a mirror surface using a chemical mechanical polishing method; and a modifying step S5 of dispersing abrasive grains that are harder than those used to form the mirror surface in the mirror surface forming process and forming a damaged layer, serving as a gettering sink for heavy metal, on the rear surface of the silicon wafer using the chemical mechanical polishing method. The thickness T5b of the damaged layer W5b in a wafer depth direction is set by the chemical mechanical polishing method in the modifying step S5 to control the gettering capability of the damaged layer.

Abstract translation: 通过对硅单晶进行切片来制造薄硅晶片的方法包括：在硅晶片的表面上形成器件结构之后，对硅晶片的后表面进行研磨以减小硅晶片的厚度的薄化步骤S3， 晶圆 使用化学机械抛光方法将硅晶片的后表面加工成镜面的镜面形成步骤S4; 以及在镜面形成工序中分散比用于形成镜面的磨粒硬的分散磨粒的改性步骤S5，并且在硅晶片的后表面上形成用作重金属的吸气槽的损伤层，使用 化学机械抛光方法。 损伤层W5b在晶片深度方向上的厚度T5b通过化学机械研磨法在修改步骤S5中设定，以控制损伤层的吸气能力。

公开(公告)号：US07545004B2

公开(公告)日：2009-06-09

申请号：US10907689

申请日：2005-04-12

Applicant: Haining S. Yang ,  Eng Hua Lim

Inventor： Haining S. Yang ,  Eng Hua Lim

IPC: H01L29/78 ,  H01L29/34

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L21/823871

Abstract: A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is deposited over portions of the second layer based on the mapping step. The exposed area of the second layer is etched to form a smooth boundary between the first layer and the second layer. The resist layer is stripped. The resulting device is an improved PFET device and NFET device with a smooth boundary between the first and second layers such that a contact can be formed at the smooth boundary without over etching other areas of the device.

Abstract translation: 一种用于制造器件的方法包括：基于沉积的第一层和第二层的垂直边缘，对掩模层的极限垂直边界条件进行映射。 基于映射步骤，掩模层沉积在第二层的部分上。 蚀刻第二层的暴露区域以在第一层和第二层之间形成平滑的边界。 剥离抗蚀剂层。 所得到的器件是改进的PFET器件和NFET器件，其在第一和第二层之间具有平滑的边界，使得可以在光滑边界处形成接触，而不会过度蚀刻器件的其它区域。

公开(公告)号：US07511309B2

公开(公告)日：2009-03-31

申请号：US11380464

申请日：2006-04-27

Applicant: Hyun-Eok Shin

Inventor： Hyun-Eok Shin

IPC: H01L29/34

CPC classification number: H01L51/5218 ,  H01L27/3244 ,  H01L27/3279 ,  H01L2251/5315 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An organic light emitting display device and a method of fabricating the same are provided, which employ an Ag alloy containing Sm, Tb, Au, and Cu to simultaneously form a source electrode, a drain electrode, and a first electrode of the organic light emitting display device for increasing the reflectivity and efficiency of the organic light emitting display device and reducing the organic light emitting display device panel size by reducing a line width of the source and drain electrodes due to the low resistance of the source and drain electrodes.

Abstract translation: 提供一种有机发光显示装置及其制造方法，其使用含有Sm，Tb，Au和Cu的Ag合金，以同时形成有机发光的源电极，漏电极和第一电极 显示装置，用于增加有机发光显示装置的反射率和效率，并且由于源极和漏极的低电阻而减小源电极和漏电极的线宽而减小有机发光显示装置面板尺寸。

公开(公告)号：US20080122037A1

公开(公告)日：2008-05-29

申请号：US11462124

申请日：2006-08-03

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L29/34 ,  H01L21/66

CPC classification number: H01L29/34 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract translation: 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。

公开(公告)号：US06949434B2

公开(公告)日：2005-09-27

申请号：US10880048

申请日：2004-06-29

Applicant: Yoshifumi Okabe ,  Masami Yamaoka ,  Akira Kuroyanagi

Inventor： Yoshifumi Okabe ,  Masami Yamaoka ,  Akira Kuroyanagi

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/304 ,  H01L21/336 ,  H01L29/06 ,  H01L29/167 ,  H01L29/34 ,  H01L29/417 ,  H01L29/45 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L21/3205 ,  H01L21/44

CPC classification number: H01L29/7802 ,  H01L21/28 ,  H01L21/28512 ,  H01L21/304 ,  H01L29/0657 ,  H01L29/167 ,  H01L29/34 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/10158 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/964 ,  Y10S438/977 ,  H01L2924/00

Abstract: A method of manufacturing a vertical semiconductor device includes preparing a semiconductor wafer which has a heavily doped semiconductor substrate and a lightly doped semiconductor layer disposed over the semiconductor substrate, forming a semiconductor element at a surface portion of the semiconductor layer, forming a first metal layer for a first electrode of the semiconductor element over the surface portion of the semiconductor layer, grinding a back of the semiconductor substrate to thin the semiconductor substrate and roughen a back surface of the semiconductor substrate, performing a wet etching upon the back surface; and forming on the back surface a second metal layer for a second electrode of the semiconductor element.

Abstract translation: 一种制造垂直半导体器件的方法包括制备半导体晶片，该半导体晶片具有重掺杂半导体衬底和设置在半导体衬底上的轻掺杂半导体层，在半导体层的表面部分形成半导体元件，形成第一金属层 在半导体层的表面部分上的半导体元件的第一电极，研磨半导体衬底的背面以使半导体衬底细化并粗糙化半导体衬底的背面，对背面进行湿式蚀刻; 以及在所述背面上形成用于所述半导体元件的第二电极的第二金属层。