公开(公告)号：US06979874B2

公开(公告)日：2005-12-27

申请号：US10283132

申请日：2002-10-30

申请人： Masana Harada

发明人： Masana Harada

IPC分类号： H01L21/329 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872 ,  H01L27/095 ,  H01L29/80

CPC分类号： H01L29/66136 ,  H01L29/0619 ,  H01L29/66356 ,  H01L29/861 ,  H01L29/872

摘要： A plurality of p anode regions are formed at one surface of an n− substrate. A trench is formed in each p anode region. An ohmic junction region is formed between an anode metallic electrode and the p anode region. The p anode region has a minimum impurity concentration at a portion near the ohmic junction region which enables ohmic contact. A cathode metallic electrode is formed at the other surface of the n− substrate with an n+ cathode region interposed. Accordingly, a semiconductor device which has an improved withstand voltage and in which the reverse recovery current is reduced can be obtained.

摘要翻译： 在正极基板的一个表面上形成多个p阳极区域。 在每个p阳极区域中形成沟槽。 在阳极金属电极和p阳极区域之间形成欧姆结区域。 p阳极区域在欧姆接合区附近的一部分具有最小的杂质浓度，能够进行欧姆接触。 阴极金属电极形成在n + SUP衬底的另一个表面，其中插入有n + +阴极区。 因此，可以获得具有改善的耐受电压并且反向恢复电流降低的半导体器件。

公开(公告)号：US06977208B2

公开(公告)日：2005-12-20

申请号：US10766460

申请日：2004-01-27

申请人： Davide Chiola

发明人： Davide Chiola

IPC分类号： H01L21/329 ,  H01L21/763 ,  H01L27/08 ,  H01L27/095 ,  H01L29/06 ,  H01L29/872 ,  H01L21/28

CPC分类号： H01L29/8725 ,  H01L21/763 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/0692 ,  H01L29/66143 ,  H01L29/872

摘要： A trench schottky diode which includes a thin insulation layer on the sidewalls of its trenches and a relatively thicker insulation layer at the bottoms of its trenches.

摘要翻译： 沟槽肖特基二极管，其在其沟槽的侧壁上包括薄的绝缘层，在其沟槽的底部包括相对较厚的绝缘层。

公开(公告)号：US20050258424A1

公开(公告)日：2005-11-24

申请号：US11079018

申请日：2005-03-10

申请人： Bernard Sautreuil ,  Michel Marty ,  Jerome Bonnouvrier ,  Jean-Francois Carpentier

发明人： Bernard Sautreuil ,  Michel Marty ,  Jerome Bonnouvrier ,  Jean-Francois Carpentier

IPC分类号： H01L21/02 ,  H01L21/329 ,  H01L27/08 ,  H01L29/92 ,  H01L29/93 ,  H01L21/00

CPC分类号： H01L27/0805 ,  H01L29/92

摘要： A capacitor made in an upper part of a semiconductor substrate, comprising at least one lightly-doped N-type semiconductor layer having its upper surface comprising a heavily-doped P-type region delimited by an insulation area, a contact of the capacitor being formed by a metal layer buried immediately under the N-type semiconductor layer and by at least one vertical metal contact crossing the semiconductor layer down to the metal layer, the contact reaching the surface of the semiconductor layer outside of the P-type region.

摘要翻译： 一种在半导体衬底的上部制造的电容器，包括至少一个轻掺杂的N型半导体层，其上表面包括由绝缘区限定的重掺杂P型区，形成电容器的接触 通过埋在N型半导体层正下方的金属层和通过半导体层向下与金属层交叉的至少一个垂直金属接触，该接触到达P型区域外部的半导体层的表面。

公开(公告)号：US20050199978A1

公开(公告)日：2005-09-15

申请号：US11045581

申请日：2005-01-31

申请人： Makoto Takayama

发明人： Makoto Takayama

IPC分类号： H01L29/872 ,  H01L21/329 ,  H01L29/47 ,  H01L29/76

CPC分类号： H01L29/872 ,  H01L29/47 ,  H01L29/66143

摘要： A problem in related art according to which an increase in leak current cannot be avoided in order to obtain a low forward voltage VF as forward voltage VF and reverse leak current IR characteristics of a Schottky barrier diode are in a trade-off relationship is hereby solved by forming a Schottky barrier diode using a metal layer comprising a Schottky metal layer of Ti including a small amount of Al. Consequently, a low reverse leak current IR can be obtained without causing a large increase in the forward voltage VF of pure Ti such that power consumption can be reduced by suppressing forward power loss and decreasing reverse power loss.

摘要翻译： 因此，为了获得正向电压VF的正向电压VF和肖特基势垒二极管的反向泄漏电流IR特性的低正向电压VF处于权衡关系中，不能避免泄漏电流的增加的现有技术的问题被解决 通过使用包含少量Al的包含Ti的肖特基金属层的金属层来形成肖特基势垒二极管。 因此，可以获得低的反向漏电流IR，而不会导致纯Ti的正向电压VF的大幅度增加，从而可以通过抑制正向功率损耗和减小反向功率损耗来降低功耗。

公开(公告)号：US06939755B1

公开(公告)日：2005-09-06

申请号：US09226216

申请日：1999-01-07

申请人： Hisashi Ohtani ,  Shunpei Yamazaki

发明人： Hisashi Ohtani ,  Shunpei Yamazaki

IPC分类号： G02F1/136 ,  C30B1/00 ,  G02F1/1368 ,  H01L21/00 ,  H01L21/20 ,  H01L21/329 ,  H01L21/336 ,  H01L21/36 ,  H01L21/84 ,  H01L29/786

CPC分类号： H01L21/02672 ,  C04B2237/366 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02686 ,  H01L21/2022 ,  H01L21/2026 ,  H01L29/66757 ,  H01L29/66765

摘要： In a method of obtaining a crystalline silicon film having high crystallinity at a low temperature and for a short time by using a catalytic element and using both a heat treatment and irradiation of laser light, a catalytic element which does not require a gettering step is used as the catalytic element for facilitating crystallization, so that a semiconductor device having high characteristics and high productivity is obtained. Specifically, a coating film of an element in group 14, such as germanium, which is the same group of the periodic table as silicon is formed on an amorphous silicon film formed on a glass substrate, a heat treatment at 550° C. for 4 hours is carried out, and further, irradiation of laser light is carried out, so that a crystalline silicon film is obtained. In the above structure, the element in group 14, which does not have a bad influence on TFT characteristics even if the element is left in the silicon film, is used, so that the semiconductor device having high characteristics and high productivity can be obtained.

摘要翻译： 通过使用催化剂元素，同时使用热处理和激光照射，在低温下得到高结晶度的结晶硅，短时间的方法，使用不需要吸气工序的催化剂元素 作为促进结晶的催化元素，从而获得具有高特性和高生产率的半导体器件。 具体地，在形成于玻璃基板上的非晶硅膜上形成与硅相同的第14族元素（例如锗）的元素周期表中的元素的涂膜，在550℃下热处理4 进行小时，进一步进行激光的照射，得到结晶硅膜。 在上述结构中，使用即使在硅膜中残留元素也不会对TFT特性造成不良影响的组14中的元素，从而可以获得具有高特性和高生产率的半导体器件。

公开(公告)号：US20050181564A1

公开(公告)日：2005-08-18

申请号：US11017468

申请日：2004-12-20

申请人： Fwu-Iuan Hshieh ,  Koon So ,  Brian Pratt

发明人： Fwu-Iuan Hshieh ,  Koon So ,  Brian Pratt

IPC分类号： H01L21/265 ,  H01L21/329 ,  H01L21/336 ,  H01L29/06 ,  H01L29/76 ,  H01L29/78 ,  H01L29/872 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66143 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.

摘要翻译： 制造半导体器件的方法包括提供具有沟槽和台面的半导体衬底。 至少一个台面具有第一和第二侧壁。 该方法包括将第二导电性的掺杂剂角度地注入到第一侧壁中，并将第二导电性的掺杂剂角度地注入第二侧壁。 通过将掺杂剂扩散到至少一个台面中，将至少一个台面转变成柱。 然后通过将第一导电性的掺杂剂角度地注入到柱的第一侧壁中，并且将第一导电类型的掺杂剂角度地注入到柱的第二侧壁中，将柱转换成列。 然后将掺杂剂扩散到柱中以提供沿相邻沟槽的深度方向定位的第一和第二掺杂区的P-N结。 最后，沟槽填充绝缘材料。

公开(公告)号：US20050170629A1

公开(公告)日：2005-08-04

申请号：US11071221

申请日：2005-03-04

申请人： John Janning

发明人： John Janning

IPC分类号： F21S4/00 ,  H01L21/329 ,  H01L21/44 ,  H01L29/866 ,  F21V21/00

CPC分类号： H01L29/866 ,  F21S4/10 ,  H01L29/66106

摘要： A process for fabricating Zener diodes that does not require the use of photomasks. An oxide layer is grown on a silicon substrate which is doped with an N-type dopant. The substrate is subsequently implanted with a P-type dopant, forming a PN junction. The substrate is then metallized for connecting the Zener diode to other circuit components. Advantageously, the substrate is scribed after ‘seeding’ and before electroless metallization. Back-to-back Zener diodes formed in this manner are used as shunt circuits across individual lamp sockets in series-wired Christmas light strings to maintain current flow to each of the lamps of the light string when one or multiple lamps fail.

摘要翻译： 制造不需要使用光掩模的齐纳二极管的工艺。 在掺杂有N型掺杂剂的硅衬底上生长氧化物层。 衬底随后用P型掺杂剂注入，形成PN结。 然后将衬底金属化以将齐纳二极管连接到其他电路部件。 有利地，在“接种”之后和在无电镀金属化之前刻划基板。 以这种方式形成的背靠背齐纳二极管被用作串联有线圣诞灯串中的各个灯插座的分路电路，以在一个或多个灯管故障时保持电流流向灯串的每个灯。

公开(公告)号：US20050162881A1

公开(公告)日：2005-07-28

申请号：US10765799

申请日：2004-01-27

申请人： James Stasiak ,  Kevin Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

发明人： James Stasiak ,  Kevin Peters ,  Jennifer Wu ,  Pavel Kornilovich ,  Yong Chen

IPC分类号： H01L21/027 ,  G03F7/00 ,  H01L21/329 ,  H01L21/8229 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/102 ,  H01L27/105 ,  H01L27/24 ,  H01L27/28 ,  H01L51/05 ,  G11C5/06

CPC分类号： B82Y10/00 ,  H01L27/1021 ,  H01L27/24 ,  Y10S977/887 ,  Y10S977/94

摘要： A memory device including a substrate, and multiple self-alignednano-rectifying elements disposed over the substrate. Each nano-rectifying element has multiple first electrode lines, and multiple device structures disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less than about 75 nanometers. The memory device also includes multiple switching elements disposed over the device structures and self-aligned in at least one direction with the device structures. In addition, the memory device includes multiple second electrode lines disposed over, electrically coupled to, and self-aligned to the switching elements, whereby a memory device is formed.

摘要翻译： 一种存储器件，包括衬底和设置在衬底上的多个自对准纳米整流元件。 每个纳米整流元件具有多个第一电极线，并且多个器件结构设置在形成多个自对准纳米整流元件的多个第一电极线上。 每个器件结构具有小于约75纳米的至少一个横向尺寸。 存储器件还包括设置在器件结构上的多个开关元件，并且在至少一个方向上与器件结构自对准。 此外，存储器件包括多个第二电极线，其布置在开关元件上方，电耦合并自对准，从而形成存储器件。

公开(公告)号：US20050158979A1

公开(公告)日：2005-07-21

申请号：US10864917

申请日：2004-06-09

申请人： Seiji Momota ,  Eiji Mochizuki

发明人： Seiji Momota ,  Eiji Mochizuki

IPC分类号： H01L21/288 ,  H01L21/3205 ,  H01L21/329 ,  H01L23/52 ,  H01L29/06 ,  H01L29/417 ,  H01L29/861 ,  H01L21/76 ,  H01L21/44

CPC分类号： H01L29/66136 ,  H01L29/417 ,  H01L29/861 ,  H01L2924/0002 ,  Y10S438/928 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device is disclosed in which a metallic deposit is stably formed on the anode side with small variation in film thickness, and plating is prevented on the cathode side without carrying out any additional processing on the cathode side. The processed anode side causes no interference in subsequent processing. Insulator films are used to cover a scribe line, as well as a field plate or an open electrode provided on a surface of a silicon substrate before Ni electroless plating of an aluminum electrode is performed to form a metallic deposit on the electrode.

摘要翻译： 公开了一种制造半导体器件的方法，其中在阳极侧稳定地形成金属沉积物，薄膜的厚度变化小，并且在阴极侧不会对阴极侧进行任何额外的处理来防止电镀。 经处理的阳极侧在后续处理中不产生干扰。 在进行铝电极的Ni化学镀以在电极上形成金属沉积物之前，使用绝缘膜覆盖划线，以及设置在硅衬底的表面上的场板或开放电极。

公开(公告)号：US20050158939A1

公开(公告)日：2005-07-21

申请号：US11067421

申请日：2005-02-25

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L21/331 ,  H01L21/329 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H01L29/732 ,  H01L29/861 ,  H01L21/336 ,  H01L23/62

CPC分类号： H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.