公开(公告)号：US20080023762A1

公开(公告)日：2008-01-31

申请号：US11881942

申请日：2007-07-30

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/82285 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835

摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

公开(公告)号：US20060157818A1

公开(公告)日：2006-07-20

申请号：US10767419

申请日：2004-01-29

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L29/00

CPC分类号： H01L29/7816 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/82285 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835

摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

公开(公告)号：US20050142724A1

公开(公告)日：2005-06-30

申请号：US11067212

申请日：2005-02-25

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L21/331 ,  H01L21/329 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H01L29/732 ,  H01L29/861 ,  H01L23/62

CPC分类号： H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

公开(公告)号：US20050023606A1

公开(公告)日：2005-02-03

申请号：US10767751

申请日：2004-01-28

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L21/762 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/82285 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835

摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

摘要翻译： 在不含外延层的基板中形成半导体器件系列。 在一个实施例中，该系列包括5V CMOS对，12V CMOS对，5V NPN，5V PNP，多种形式的横向沟槽MOSFET和30V侧向N沟道DMOS。 每个装置在横向和垂直方面非常紧凑，并且可以与基板中的所有其它装置完全隔离。

公开(公告)号：US20090108561A1

公开(公告)日：2009-04-30

申请号：US12252942

申请日：2008-10-16

申请人： Benjamin Barber ,  Richard Bordoni ,  Julia Brady ,  Max Brivic ,  Michael Cornell ,  James Doerhoff ,  Jonathan Goldszmidt ,  Jeffrey Rovernpor ,  Sahib Singh ,  David B. Ponterio ,  Ahron Rosenfeld

发明人： Benjamin Barber ,  Richard Bordoni ,  Julia Brady ,  Max Brivic ,  Michael Cornell ,  James Doerhoff ,  Jonathan Goldszmidt ,  Jeffrey Rovernpor ,  Sahib Singh ,  David B. Ponterio ,  Ahron Rosenfeld

IPC分类号： A61G5/10 ,  B63B27/14

CPC分类号： A61G5/06 ,  A61G3/061

摘要： A curb climbing wheelchair system having left and right side attachments are designed to be attached to left and right side portions, respectively, of a standard wheelchair to enable a wheelchair occupant to climb a curb, bump or other obstruction without the aid of another individual. Each attachment includes a ramp extending from a telescoping arm that is designed to be attached, via a clamping system, to one side of the wheelchair. When not in use, the ramps are folded and stowed away on the sides of the wheelchair. During use, the ends of the ramps are placed on the curb to allow the wheelchair occupant to roll up the curb. To retrieve the ramps (now disposed behind the wheelchair), the wheelchair occupant moves the telescoping arms, if necessary with the aid of an attached circular handle, to lift the ramps thus allowing the wheelchair occupant to grab the ramps. The retrieved ramps then are stowed away until needed.

摘要翻译： 具有左侧和右侧附件的路缘攀爬轮椅系统被设计成分别附接到标准轮椅的左侧和右侧部分，以使得轮椅乘员能够在没有另一个人的帮助的情况下爬上路缘，撞击物或其他障碍物。 每个附件包括从伸缩臂延伸的斜坡，其设计成经由夹紧系统连接到轮椅的一侧。 当不使用时，斜坡被折叠并收起在轮椅的两侧。 在使用过程中，坡道的末端被放置在路边，以便轮椅乘员卷起路缘。 为了检索斜坡（现在位于轮椅后面），轮椅乘员在必要时借助于附接的圆形手柄移动伸缩臂，以提升坡道，从而允许轮椅乘员抓住坡道。 然后将检索到的斜坡收起，直到需要。

公开(公告)号：US20070272986A1

公开(公告)日：2007-11-29

申请号：US11881841

申请日：2007-07-30

申请人： Richard Williams ,  Michael Cornell ,  Wai Chen

发明人： Richard Williams ,  Michael Cornell ,  Wai Chen

IPC分类号： H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/82285 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835

摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

公开(公告)号：US20060246650A1

公开(公告)日：2006-11-02

申请号：US11452724

申请日：2006-06-13

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L21/8238

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7827

摘要： In a trench-gated MOSFET including an epitaxial layer over a substrate of like conductivity and trenches containing thick bottom oxide, sidewall gate oxide, and conductive gates, body regions of the complementary conductivity are shallower than the gates, and clamp regions are deeper and more heavily doped than the body regions but shallower than the trenches. Zener junctions clamp a drain-source voltage lower than the FPI breakdown of body junctions near the trenches, but the zener junctions, being shallower than the trenches, avoid undue degradation of the maximum drain-source voltage. The epitaxial layer may have a dopant concentration that increases step-wise or continuously with depth. Chained implants of the body and clamp regions permits accurate control of dopant concentrations and of junction depth and position. Alternative fabrication processes permit implantation of the body and clamp regions before gate bus formation or through the gate bus after gate bus formation.

公开(公告)号：US20060223257A1

公开(公告)日：2006-10-05

申请号：US11278771

申请日：2006-04-05

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall and which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

摘要翻译： 通过将掺杂剂注入到不包括外延层的半导体衬底中来形成用于电绝缘半导体器件的结构。 在植入后，该结构暴露于非常有限的热预算，使得掺杂剂不显着扩散。 结果，隔离结构的尺寸受限制和限定，从而允许比使用包括外延层生长和掺杂剂扩散的常规工艺可获得更高的堆积密度。 在一组实施例中，隔离结构包括深层和侧壁，并且它们一起形成围绕可以形成隔离半导体器件的封闭区域的杯形结构。 侧壁可以由不同能量的一系列脉冲植入物形成，由此产生一叠重叠的注入区域。

公开(公告)号：US20060014349A1

公开(公告)日：2006-01-19

申请号：US11228741

申请日：2005-09-15

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L21/336 ,  H01L21/461

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66734 ,  H01L29/7811

摘要： Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

摘要翻译： 功率MOSFET的功率MOSFET和制造工艺在沟槽内使用连续的导电栅极结构，以避免当栅极总线延伸到衬底表面之上时引起的器件拓扑引起的问题。 器件沟槽中的栅极总线沟槽和/或栅极结构可以包含金属/硅化物以降低电阻，其中多晶硅层围绕金属/硅化物，以防止金属原子穿过器件沟槽中的栅极氧化物。 CMP工艺可以去除过量的多晶硅和金属，并平坦化导电栅极结构和/或覆盖绝缘层。 该过程与在有源器件区域中形成自对准或常规触点的工艺兼容。

公开(公告)号：US20050194643A1

公开(公告)日：2005-09-08

申请号：US11123448

申请日：2005-05-05

申请人： Richard Williams ,  Michael Cornell ,  Wai Tien Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Tien Chan

IPC分类号： H01L23/485 ,  H01L23/495 ,  H01L23/58 ,  H01L23/62 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L23/60 ,  H01L22/32 ,  H01L23/49562 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0266 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05138 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  Y10S257/904 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.