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    Isolated drain-centric lateral MOSFET
    4.
    发明申请
    Isolated drain-centric lateral MOSFET 有权
    隔离漏极为中心的侧向MOSFET

    公开(公告)号：US20110012196A1

    公开(公告)日：2011-01-20

    申请号：US12807675

    申请日：2010-09-10

    申请人： Richard K. Williams ,  Donald Ray Disney ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Donald Ray Disney ,  Wai Tien Chan

    IPC分类号： H01L29/735

    CPC分类号： H01L29/735 ,  H01L21/761 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/092 ,  H01L29/7322 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET is drain-centric, with the source region and a dielectric-filled trench surrounding the drain region.

    摘要翻译： 形成在第一导电类型的衬底中的横向MOSFET包括形成在衬底的表面上的栅极电介质层顶部的栅极，第二导电类型的漏极区域，第二导电类型的源极区域和主体区域 的第一导电类型在栅极下延伸。 体区域可以具有非单调垂直掺杂分布，其中位于衬底中的部分位于比衬底中较浅的部分具有更高的掺杂浓度的部分。 横向MOSFET是以漏极为中心的，源极区和围绕漏极区的电介质填充沟槽。

    Methods of fabricating isolation structures in epi-less substrate
    6.
    发明授权
    Methods of fabricating isolation structures in epi-less substrate 有权
    在无外层衬底中制​​造隔离结构的方法

    公开(公告)号：US07666756B2

    公开(公告)日：2010-02-23

    申请号：US10918314

    申请日：2004-08-14

    申请人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    IPC分类号： H01L21/76

    CPC分类号： H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

    摘要翻译： 通过将掺杂剂注入到不包括外延层的半导体衬底中来形成用于电绝缘半导体器件的结构。 在植入后，该结构暴露于非常有限的热预算，使得掺杂剂不显着扩散。 结果，隔离结构的尺寸受限制和限定，从而允许比使用包括外延层生长和掺杂剂扩散的常规工艺可获得的更高的堆积密度。 在一组实施例中，隔离结构包括深层和侧壁，其一起形成围绕可以形成隔离半导体器件的封闭区域的杯形结构。 侧壁可以由不同能量的一系列脉冲植入物形成，由此产生一叠重叠的注入区域。

    Method of fabricating isolated semiconductor devices in epi-less substrate
    10.
    发明授权
    Method of fabricating isolated semiconductor devices in epi-less substrate 有权
    在无外壳衬底中制造隔离半导体器件的方法

    公开(公告)号：US07279378B2

    公开(公告)日：2007-10-09

    申请号：US11067248

    申请日：2005-02-25

    申请人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    IPC分类号： H01L21/8238 ,  H01L21/425

    CPC分类号： H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

    摘要翻译： 通过将掺杂剂注入到不包括外延层的半导体衬底中来形成用于电绝缘半导体器件的结构。 在植入后，该结构暴露于非常有限的热预算，使得掺杂剂不显着扩散。 结果，隔离结构的尺寸受限制和限定，从而允许比使用包括外延层生长和掺杂剂扩散的常规工艺可获得更高的堆积密度。 在一组实施例中，隔离结构包括深层和侧壁，其一起形成围绕可以形成隔离半导体器件的封闭区域的杯形结构。 侧壁可以由不同能量的一系列脉冲植入物形成，由此产生一叠重叠的注入区域。