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    Methods of fabricating isolation structures in epi-less substrate
    1.
    发明授权
    Methods of fabricating isolation structures in epi-less substrate 有权
    在无外层衬底中制​​造隔离结构的方法

    公开(公告)号：US07666756B2

    公开(公告)日：2010-02-23

    申请号：US10918314

    申请日：2004-08-14

    申请人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    IPC分类号： H01L21/76

    CPC分类号： H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

    摘要翻译： 通过将掺杂剂注入到不包括外延层的半导体衬底中来形成用于电绝缘半导体器件的结构。 在植入后，该结构暴露于非常有限的热预算，使得掺杂剂不显着扩散。 结果，隔离结构的尺寸受限制和限定，从而允许比使用包括外延层生长和掺杂剂扩散的常规工艺可获得的更高的堆积密度。 在一组实施例中，隔离结构包括深层和侧壁，其一起形成围绕可以形成隔离半导体器件的封闭区域的杯形结构。 侧壁可以由不同能量的一系列脉冲植入物形成，由此产生一叠重叠的注入区域。

    Method of fabricating isolated semiconductor devices in epi-less substrate
    4.
    发明授权
    Method of fabricating isolated semiconductor devices in epi-less substrate 有权
    在无外壳衬底中制造隔离半导体器件的方法

    公开(公告)号：US07279378B2

    公开(公告)日：2007-10-09

    申请号：US11067248

    申请日：2005-02-25

    申请人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    IPC分类号： H01L21/8238 ,  H01L21/425

    CPC分类号： H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

    摘要翻译： 通过将掺杂剂注入到不包括外延层的半导体衬底中来形成用于电绝缘半导体器件的结构。 在植入后，该结构暴露于非常有限的热预算，使得掺杂剂不显着扩散。 结果，隔离结构的尺寸受限制和限定，从而允许比使用包括外延层生长和掺杂剂扩散的常规工艺可获得更高的堆积密度。 在一组实施例中，隔离结构包括深层和侧壁，其一起形成围绕可以形成隔离半导体器件的封闭区域的杯形结构。 侧壁可以由不同能量的一系列脉冲植入物形成，由此产生一叠重叠的注入区域。

    Trench-constrained isolation diffusion for integrated circuit die
    6.
    发明授权
    Trench-constrained isolation diffusion for integrated circuit die 有权
    用于集成电路管芯的沟槽限制隔离扩散

    公开(公告)号：US07834416B2

    公开(公告)日：2010-11-16

    申请号：US12221105

    申请日：2008-07-31

    申请人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    IPC分类号： H01L21/76

    CPC分类号： H01L27/0826 ,  H01L21/8224 ,  H01L21/82285 ,  H01L27/0821 ,  H01L29/6625 ,  H01L29/66272 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achieve deep diffusions with a minimal thermal budget.

    摘要翻译： 半导体衬底包括填充有电介质材料的一对沟槽。 引入到沟槽之间的台面中的掺杂剂被限制为当衬底经受热处理时横向扩散。 因此，半导体器件可以在衬底上更紧密地间隔开，并且可以增加器件的封装密度。 另外，沟槽约束掺杂区域比无约束扩散更快更深地扩散，从而减少完成所需深度扩散所需的时间和温度。 该技术可以用于诸如双极晶体管的半导体器件以及将器件彼此电隔离的隔离区域。 在一组实施例中，在外延层和衬底之间的界面处，在台面的通常低于掺杂剂的位置处形成掩埋层。 当衬底经受热处理时，掩埋层向上扩散，台面中的掺杂剂向下扩散直到两个掺杂剂合并形成从外延层的表面向掩埋层向下延伸的隔离区域或沉降片。 在另一个实施方案中，掺杂剂以高达几MeV的高能量注入电介质填充的沟槽之间，然后扩散，结合深度注入和沟槽约束扩散的优点，以最小的热预算实现深扩散。

    Method of fabricating trench-constrained isolation diffusion for semiconductor devices
    7.
    发明授权
    Method of fabricating trench-constrained isolation diffusion for semiconductor devices 有权
    制造用于半导体器件的沟槽约束隔离扩散的方法

    公开(公告)号：US07517748B2

    公开(公告)日：2009-04-14

    申请号：US11203789

    申请日：2005-08-15

    申请人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/0826 ,  H01L21/8224 ,  H01L21/82285 ,  H01L27/0821 ,  H01L29/6625 ,  H01L29/66272 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achieve deep diffusions with a minimal thermal budget.

    摘要翻译： 半导体衬底包括填充有电介质材料的一对沟槽。 引入到沟槽之间的台面中的掺杂剂被限制为当衬底经受热处理时横向扩散。 因此，半导体器件可以在衬底上更紧密地间隔开，并且可以增加器件的封装密度。 另外，沟槽约束掺杂区域比无约束扩散更快更深地扩散，从而减少完成所需深度扩散所需的时间和温度。 该技术可以用于诸如双极晶体管的半导体器件以及将器件彼此电隔离的隔离区域。 在一组实施例中，在外延层和衬底之间的界面处，在台面的通常低于掺杂剂的位置处形成掩埋层。 当衬底经受热处理时，掩埋层向上扩散，台面中的掺杂剂向下扩散直到两个掺杂剂合并形成从外延层的表面向掩埋层向下延伸的隔离区域或沉降片。 在另一个实施方案中，掺杂剂以高达几MeV的高能量注入电介质填充的沟槽之间，然后扩散，结合深度注入和沟槽约束扩散的优点，以最小的热预算实现深扩散。

    Method of fabricating isolated semiconductor devices in epi-less substrate
    8.
    发明授权
    Method of fabricating isolated semiconductor devices in epi-less substrate 有权
    在无外壳衬底中制造隔离半导体器件的方法

    公开(公告)号：US07329583B2

    公开(公告)日：2008-02-12

    申请号：US11067421

    申请日：2005-02-25

    申请人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    发明人： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

    摘要翻译： 通过将掺杂剂注入到不包括外延层的半导体衬底中来形成用于电绝缘半导体器件的结构。 在植入后，该结构暴露于非常有限的热预算，使得掺杂剂不显着扩散。 结果，隔离结构的尺寸受限制和限定，从而允许比使用包括外延层生长和掺杂剂扩散的常规工艺可获得更高的堆积密度。 在一组实施例中，隔离结构包括深层和侧壁，其一起形成围绕可以形成隔离半导体器件的封闭区域的杯形结构。 侧壁可以由不同能量的一系列脉冲植入物形成，由此产生一叠重叠的注入区域。