公开(公告)号：US07265434B2

公开(公告)日：2007-09-04

申请号：US10767419

申请日：2004-01-29

Applicant: Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

Inventor： Richard K. Williams ,  Michael E. Cornell ,  Wai Tien Chan

IPC: H01L27/82 ,  H01L27/102 ,  H01L29/72

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/82285 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

公开(公告)号：US06953981B1

公开(公告)日：2005-10-11

申请号：US09500994

申请日：2000-02-09

Applicant: Ted Johansson ,  Arne Rydin ,  Christian Nyström

Inventor： Ted Johansson ,  Arne Rydin ,  Christian Nyström

IPC: H01L21/331 ,  H01L23/48 ,  H01L29/73 ,  H01L29/732 ,  H01L29/00 ,  H01L27/82 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11 ,  H01L23/52 ,  H01L23/04 ,  H01L23/34

CPC classification number: H01L23/535 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: The present invention relates to a semiconductor device arranged at a surface of a semiconductor substrate having an initial doping having an electrical connection comprising at least one plug made of a material with a high conductivity, especially a material other than the substrate, especially a metal plug, between said initially doped substrate and said surface of the substrate. The device has at least one ground connection arranged to be connected to a ground pin on a package. The ground connection is arranged to be connected to said ground pin using said electrical connection, where the initially doped substrate is arranged to be connected to said ground pin via a reverse side of the substrate, opposite said surface, and thereby being arranged to establish a connection between said ground connection and said ground pin.

Abstract translation: 本发明涉及一种半导体器件，其布置在具有初始掺杂的半导体衬底的表面上，该初始掺杂具有电连接，该电连接包括至少一个由具有高导电性的材料制成的插塞，特别是除衬底之外的材料，特别是金属插塞 在所述初始掺杂的衬底和衬底的所述表面之间。 该装置具有布置成连接到封装上的接地引脚的至少一个接地连接。 接地连接被布置成使用所述电连接器连接到所述接地引脚，其中初始掺杂衬底被布置成经由衬底的与所述表面相对的背面连接到所述接地引脚，并且由此被布置成建立 所述接地连接和所述接地引脚之间的连接。

公开(公告)号：US07119416B1

公开(公告)日：2006-10-10

申请号：US11169444

申请日：2005-06-29

Applicant: Thomas N. Adam ,  Kevin K. Chan ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu ,  Beth Ann Rainey ,  Kathryn T. Schonenberg

Inventor： Thomas N. Adam ,  Kevin K. Chan ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu ,  Beth Ann Rainey ,  Kathryn T. Schonenberg

IPC: H01L27/82 ,  H01L29/70

CPC classification number: H01L29/7378 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287

Abstract: The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

公开(公告)号：US5258642A

公开(公告)日：1993-11-02

申请号：US911746

申请日：1992-07-10

Applicant: Shunji Nakamura

Inventor： Shunji Nakamura

IPC: H01L21/8222 ,  H01L21/285 ,  H01L21/331 ,  H01L21/335 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L29/772 ,  H01L29/786 ,  H01L29/80 ,  H01L29/00 ,  H01L27/102 ,  H01L27/82

CPC classification number: H01L29/78696 ,  H01L21/28525 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66287 ,  H01L29/66416 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7722 ,  Y10S148/011

Abstract: Semiconductor devices having a reduced parasitic capacitance while having a maximum acceptable current similar to those of prior devices, and a method of manufacturing thereof are disclosed. The inventive device has a hole at the bottom of which an insulating film separated from the hole walls is located, a semiconductor film being present in the hole, which is connected to the semiconductor substrate adjacent to the insulating film and a conductor film constituting a portion of the hole wall, and extends onto the insulating film so as to cover at least part of the film.

Abstract translation: 公开了具有减小的寄生电容，同时具有与现有器件相似的最大可接受电流的半导体器件及其制造方法。 本发明的装置在其底部具有与孔壁分离的绝缘膜的孔，存在于孔中的半导体膜连接到与绝缘膜相邻的半导体衬底和构成一部分的导体膜 的孔壁，并延伸到绝缘膜上以覆盖膜的至少一部分。

公开(公告)号：US07253498B2

公开(公告)日：2007-08-07

申请号：US10885250

申请日：2004-07-06

Applicant: Ranadeep Dutta

Inventor： Ranadeep Dutta

IPC: H01L27/82

CPC classification number: H01L29/73 ,  H01L29/0692

Abstract: The present invention is generally directed to bipolar transistors with geometry optimized for device performance and various methods of making same. In one illustrative embodiment, the device includes a substrate, an intrinsic base region formed in the substrate, a continuous emitter region formed within the intrinsic base region, the emitter region having a plurality of substantially hexagonal shaped openings defined therein, and a plurality of extrinsic base regions formed in the substrate, wherein each of the extrinsic base regions is positioned within an area defined by one of the plurality of substantially hexagonal shaped openings.

Abstract translation: 本发明一般涉及具有针对器件性能优化的几何形状的双极晶体管及其制造方法。 在一个说明性实施例中，器件包括衬底，形成在衬底中的本征基极区域，形成在本征基极区域内的连续发射极区域，发射极区域具有限定在其中的多个基本上六边形形状的开口，以及多个外部 形成在基板中的基部区域，其中每个非本征基极区域位于由多个基本六边形形状的开口之一限定的区域内。

公开(公告)号：US06906399B2

公开(公告)日：2005-06-14

申请号：US10287034

申请日：2002-11-04

Applicant: John R. Fruth ,  Scott B. Kesler

Inventor： John R. Fruth ,  Scott B. Kesler

IPC: G01K7/01 ,  H01L29/739 ,  H01L29/78 ,  H01L27/82

CPC classification number: H01L29/7804 ,  G01K7/01 ,  H01L29/0696 ,  H01L29/7395

Abstract: An integrated circuit (10) includes a thermal sensing device (20) and a power-switching device (12) such as an IGBT. The power device (12) is fabricated in a conventional manner on a semiconductor substrate, and the thermal sensing device (20) is fabricated on an electrical insulation layer (74) formed over the substrate. The thermal sensing device (20) may be provided in the form of a number of series-connected polysilicon diodes (D1-D3) positioned adjacent to the power device (12) such that the operating temperature of the thermal sensing device (20) is near that of the power device (12). In response to an input current IC, the thermal sensing device (20) produces an output voltage (VD) that is substantially linear with surface die temperature, and which reacts rapidly to changes in surface die temperature. The thermal sensing device (20) is completely electrically isolated from the power device, thereby eliminating any electrical interaction therebetween.

Abstract translation: 集成电路（10）包括热感测装置（20）和诸如IGBT的功率开关装置（12）。 功率器件（12）以常规方式制造在半导体衬底上，并且热感测器件（20）制造在形成在衬底上的电绝缘层（74）上。 热感测装置（20）可以以邻近功率装置（12）定位的多个串联多晶硅二极管（D 1 -D 3）的形式提供，使得热感测装置（20）的工作温度 ）接近功率器件（12）的功率器件。 响应于输入电流I C C，热感测装置（20）产生与表面模头温度基本上线性的输出电压（V SUB D），并且其响应于 迅速改变表面模头温度。 热感测装置（20）与动力装置完全电绝缘，从而消除它们之间的任何电气相互作用。

公开(公告)号：US5986323A

公开(公告)日：1999-11-16

申请号：US549267

申请日：1995-10-27

Applicant: Raffaele Zambrano ,  Giuseppe Fallico

Inventor： Raffaele Zambrano ,  Giuseppe Fallico

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/423 ,  H01L29/732 ,  H01L27/82 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/42304

Abstract: A high-frequency bipolar transistor structure includes a base region of a first conductivity type formed in a silicon layer of a second conductivity type, the base region comprising an intrinsic base region surrounded by an extrinsic base region, an emitter region of the second conductivity type formed inside the intrinsic base region, the extrinsic base region and the emitter region being contacted by a first polysilicon layer and a second polysilicon layer respectively. The first and the second polysilicon layers are respectively contacted by a base metal electrode and an emitter metal electrode. Between the extrinsic base region and the first polysilicon layer, a silicide layer is provided to reduce the extrinsic base resistance of the bipolar transistor.

Abstract translation: 高频双极晶体管结构包括形成在第二导电类型的硅层中的第一导电类型的基极区域，该基极区域包括被外部基极区域包围的本征基极区域，第二导电类型的发射极区域 形成在本征基区内，外基极区和发射极区分别与第一多晶硅层和第二多晶硅层接触。 第一和第二多晶硅层分别由基底金属电极和发射极金属电极接触。 在非本征基极区域和第一多晶硅层之间，提供硅化物层以降低双极晶体管的外部基极电阻。