公开(公告)号：US08921190B2

公开(公告)日：2014-12-30

申请号：US12099175

申请日：2008-04-08

Applicant: Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

Inventor： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7834 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/423 ,  H01L29/66575

Abstract: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

Abstract translation: 提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。 该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。 有源区具有不同于第一导电类型的第二导电类型。 接触区域与有源区域电接触。 该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

公开(公告)号：US08237191B2

公开(公告)日：2012-08-07

申请号：US12539284

申请日：2009-08-11

Applicant: James S. Dunn ,  Alvin J. Joseph ,  Anthony K. Stamper

Inventor： James S. Dunn ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L27/06 ,  H01L21/8248

CPC classification number: H01L29/7378

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract translation: 提供半导体结构和制造半导体的方法涉及异质结双极晶体管。 该方法包括在相同布线层上形成由金属线连接的两个器件。 两个器件中的第一个的金属线通过在铜布线结构上选择性地形成金属覆盖层而形成。

公开(公告)号：US20120168817A1

公开(公告)日：2012-07-05

申请号：US13238414

申请日：2011-09-21

Applicant: Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

Inventor： Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

IPC: H01L27/088 ,  H01L21/76 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/7436 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/785

Abstract: Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.

Abstract translation: 公开了具有高漏极对体击穿电压的横向延伸漏极，金属氧化物半导体，场效应晶体管（LEDMOSFET）的实施例。 离散导电场（CF）板与漏极漂移区的相对侧相邻，每侧具有成角度的侧壁，使得漏极漂移区和CF板之间的区域沿着漏极漂移区的长度具有连续增加的宽度， 沟道区到漏极区。 CF板可以包括与漏极漂移区相同的半导体主体内的多晶硅或金属结构或掺杂剂注入区。 CF板和漏极漂移区域之间的区域可以包括与漏极漂移区域相同的半导体本体内的锥形介质区域或者替代地，锥形耗尽区域。 还公开了用于形成LEDMOSFET的方法的实施例和结合了这种LEDMOSFET的可控硅整流器（SCR）的实施例。

公开(公告)号：US20110127529A1

公开(公告)日：2011-06-02

申请号：US12627343

申请日：2009-11-30

Applicant: Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

Inventor： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract translation: 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US20110121369A1

公开(公告)日：2011-05-26

申请号：US12622733

申请日：2009-11-20

Applicant: Brent A. Anderson ,  Alvin J. Joseph ,  Edward J. Nowak

Inventor： Brent A. Anderson ,  Alvin J. Joseph ,  Edward J. Nowak

IPC: H01L27/12 ,  G06F17/50

CPC classification number: H01L21/845 ,  G06F17/5045 ,  H01L27/1211 ,  H01L29/045

Abstract: An integrated circuit (IC) includes a fin field effect transistor (FinFET) radio frequency (RF) switch; and a planar complementary metal-oxide semiconductor field effect transistor (MOSFET). The planar MOSFET has a channel on a wafer plane and the FinFET RF switch has a channel on a fin plane. The FinFET RF switch and the planar MOSFET can be oriented at approximately 45° with respect to one another.

Abstract translation: 集成电路（IC）包括鳍状场效应晶体管（FinFET）射频（RF）开关; 和平面互补金属氧化物半导体场效应晶体管（MOSFET）。 平面MOSFET在<100>晶片平面上具有通道，并且FinFET RF开关在<100>鳍平面上具有通道。 FinFET RF开关和平面MOSFET可以相对于彼此大约45°取向。

公开(公告)号：US07898061B2

公开(公告)日：2011-03-01

申请号：US11741436

申请日：2007-04-27

Applicant: James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

Inventor： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

IPC: H01L29/73

CPC classification number: H01L29/7371 ,  H01L27/0823 ,  H01L29/66242

Abstract: A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.

Abstract translation: 提供了形成其中具有两个不同应变的半导体器件的方法。 该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。 第一或第二应变中的任一种可以是拉伸的或压缩的。 此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。 特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

公开(公告)号：US20100248432A1

公开(公告)日：2010-09-30

申请号：US12795108

申请日：2010-06-07

Applicant: Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

Inventor： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC: H01L21/84 ,  G06F17/50

CPC classification number: H01L29/93

Abstract: Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.

Abstract translation: 形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。 通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。 反渗透定义了超突变p-n结。 在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。

公开(公告)号：US07804119B2

公开(公告)日：2010-09-28

申请号：US12099316

申请日：2008-04-08

Applicant: Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

Inventor： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC: H01L27/108

CPC classification number: H01L29/93

Abstract: Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.

Abstract translation: 具有超突变p-n结的器件结构，形成超突变p-n结的方法以及包含具有超突变p-n结的器件结构的集成电路的设计结构。 通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。 反渗透定义了超突变p-n结。 在离子注入期间，在器件层的顶表面上承载的栅极结构作为硬掩模进行操作，以有助于限定超突变n结的横向边界。

公开(公告)号：US07625792B2

公开(公告)日：2009-12-01

申请号：US10599938

申请日：2005-04-06

Applicant: Peter J. Geiss ,  Alvin J. Joseph ,  Qizhi Liu ,  Bradley A. Orner

Inventor： Peter J. Geiss ,  Alvin J. Joseph ,  Qizhi Liu ,  Bradley A. Orner

IPC: H01L21/8238

CPC classification number: H01L29/0804 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

Abstract translation: 公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极，集电极之上的本征基极，与集电极相邻的浅沟槽隔离区，在本征基极之上的凸起的外部基极，T形发射极 在外部基极之上，邻近发射极的间隔物和通过间隔物与发射极分离的硅化物层。

公开(公告)号：US20090020851A1

公开(公告)日：2009-01-22

申请号：US11614757

申请日：2006-12-21

Applicant: Qizhi Liu ,  Peter B. Gray ,  Alvin J. Joseph

Inventor： Qizhi Liu ,  Peter B. Gray ,  Alvin J. Joseph

IPC: H01L21/331 ,  H01L29/73

CPC classification number: H01L29/41708 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7371

Abstract: A method of fabricating an heterojunction bipolar transistor (HBT) structure in a bipolar complementary metal-oxide-semiconductor (BiCMOS) process selectively thickens an oxide layer overlying a base region in areas that are not covered by a temporary emitter and spacers such that the temporary emitter can be removed and the base-emitter junction can be exposed without also completely removing the oxide overlying the areas of the base region that are not covered by the temporary emitter or spacers. As a result, a photomask is not required to remove the temporary emitter and to expose the base-emitter junction.

Abstract translation: 在双极互补金属氧化物半导体（BiCMOS）工艺中制造异质结双极晶体管（HBT）结构的方法在未被临时发射极和间隔物覆盖的区域中的基极区域上选择性地增厚氧化物层，使得临时 可以去除发射极，并且可以暴露基极 - 发射极结，而不会完全去除覆盖在未被临时发射极或间隔物覆盖的基极区域的区域上的氧化物。 结果，不需要光掩模去除临时发射体并露出基极 - 发射极结。