公开(公告)号：US08928068B2

公开(公告)日：2015-01-06

申请号：US13857136

申请日：2013-04-04

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： Stuart B. Molin ,  Michael A. Stuber

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L21/683

CPC分类号： H01L27/1203 ,  H01L21/6835 ,  H01L21/823487 ,  H01L21/84 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

摘要： A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

摘要翻译： 垂直半导体器件（例如垂直功率器件，IGBT器件，垂直双极晶体管，UMOS器件或GTO晶闸管）形成有有源半导体区域，其中已经制造了多个半导体结构以形成有源 器件，并且在其下方已经去除了衬底材料的至少一部分以隔离有源器件，以暴露用于底侧电连接的半导体结构中的至少一个并且增强散热。 半导体结构中的至少一个优选地与有源半导体区域的底侧的电极接触。

公开(公告)号：US08859395B2

公开(公告)日：2014-10-14

申请号：US12627957

申请日：2009-11-30

申请人： Roger A. Fratti ,  Warren K. Waskiewicz

发明人： Roger A. Fratti ,  Warren K. Waskiewicz

IPC分类号： H01L21/30 ,  H01L21/306 ,  H01L23/31 ,  H01L29/66

CPC分类号： H01L29/66234 ,  H01L21/30625 ,  H01L23/3171 ,  H01L29/66363 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00

摘要： Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit.

摘要翻译： 提供了用于处理功率晶体管器件的技术。 在一个方面，包括形成在基板上的器件膜的功率晶体管器件的曲率通过使衬底变薄来控制，该器件具有至少部分归因于薄化步骤的总残余应力，并且将应力补偿层施加到 所述器件膜的表面，所述应力补偿层具有足以抵消所述器件的总残余应力的至少一部分的拉伸应力。 所得的功率晶体管器件可以是集成电路的一部分。

公开(公告)号：US08835975B1

公开(公告)日：2014-09-16

申请号：US13892226

申请日：2013-05-10

申请人： IXYS Corporation

发明人： Subhas Chandra Bose Jayappa Veeramma

IPC分类号： H01L29/36 ,  H01L29/74 ,  H01L31/111 ,  H01L29/32 ,  H01L29/87 ,  H01L29/66

CPC分类号： H01L29/66363 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/41716 ,  H01L29/74 ,  H01L29/87

摘要： In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.

摘要翻译： 在第一实施例中，超快断路二极管具有小于0.3微秒的导通时间TON，其中正向断流电压大于+400伏特并且变化小于每十摄氏度变化的1％。 在第二实施例中，分解二极管的反向击穿电压绝对值大于正向击穿电压大于+400伏特的正向击穿电压。 在第三实施例中，串联连接的断路二极管管芯与电阻器串一起提供在封装电路中。 即使封装电路不包括离散的高压反向击穿二极管，封装的电路就像具有大的正向断开电压和相当大的反向击穿电压的单个断开二极管。 封装电路可用于向电压保护电路中的晶闸管提供触发电流。

公开(公告)号：US20140225158A1

公开(公告)日：2014-08-14

申请号：US13763374

申请日：2013-02-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY,

发明人： Hsi-Yu Kuo ,  Chi-Kuang Chen

IPC分类号： H01L29/74 ,  H01L29/66

CPC分类号： H01L29/74 ,  H01L27/0262 ,  H01L29/66363

摘要： Methods and apparatus are disclosed for ESD protection circuits. An ESD protection circuit may comprise a lateral silicon controlled rectifier (SCR) circuit and a lateral PNP bipolar junction transistor (BJT) circuit. The SCR circuit comprises a first region on an n type buried layer (NBL), a second region on the NBL, a fourth region formed within the first region, and a fifth region formed within the second region. The PNP circuit comprises the second region on the NBL, a third region on the NBL, and a sixth region formed within the third region. The first region is the 1st N node of the SCR circuit and is connected with the base of the PNP circuit, which is the third region, by the NBL, and the 2nd P node of the SCR circuit is shared with the collector of the PNP circuit.

摘要翻译： 公开了用于ESD保护电路的方法和装置。 ESD保护电路可以包括横向可控硅整流器（SCR）电路和横向PNP双极结型晶体管（BJT）电路。 SCR电路包括n型掩埋层（NBL）上的第一区域，NBL上的第二区域，形成在第一区域内的第四区域和形成在第二区域内的第五区域。 PNP电路包括NBL上的第二区域，NBL上的第三区域和形成在第三区域内的第六区域。 第一个区域是SCR电路的第一个N节点，并且通过NBL与作为第三个区域的PNP电路的基极连接，并且SCR电路的第二个P节点与PNP的集电极共享 电路。

公开(公告)号：US20140225157A1

公开(公告)日：2014-08-14

申请号：US13763337

申请日：2013-02-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsi-Yu Kuo ,  Chi-Kuang Chen

IPC分类号： H01L29/74 ,  H01L29/66

CPC分类号： H01L29/74 ,  H01L27/0259 ,  H01L29/66363

摘要： Methods and apparatus are disclosed for ESD protection circuits. An ESD protection circuit may comprise a first region of an n type material, a second region of a p type material adjacent to the first region, a third region of an n type material within the second region and separated from the first region, and a fourth region of a p type material within the third region. There may be multiple parts within the first region and the second region, made of different n type or p type materials. An ESD protection circuit may further comprise a fifth region of a p type material, contained within the first region.

摘要翻译： 公开了用于ESD保护电路的方法和装置。 ESD保护电路可以包括n型材料的第一区域，邻近第一区域的ap型材料的第二区域，在第二区域内的与第一区域分离的n型材料的第三区域，以及第四区域 第三区域内的ap型材料区域。 在第一区域和第二区域内可以有多个部件，由不同的n型或p型材料制成。 ESD保护电路还可以包括在第一区域内的p型材料的第五区域。

公开(公告)号：US20140131765A1

公开(公告)日：2014-05-15

申请号：US13678347

申请日：2012-11-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, L

发明人： Tsung-Che Tsai ,  Yi-Feng Chang ,  Jam-Wem Lee

IPC分类号： H01L23/60 ,  H01L29/66

CPC分类号： H01L29/66363 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0886 ,  H01L29/73 ,  H01L29/7391 ,  H01L29/7436

摘要： A device includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. The device further includes a first node and a second node, and an Electro-Static Discharge (ESD) device coupled between the first node and the second node. The ESD device includes a semiconductor fin adjacent to and over a top surface of the insulation region. The ESD device is configured to, in response to an ESD transient on the first node, conduct a current from the first node to the second node.

摘要翻译： 一种器件包括半导体衬底和从半导体衬底的顶表面延伸到半导体衬底中的绝缘区域。 该设备还包括第一节点和第二节点以及耦合在第一节点和第二节点之间的静电放电（ESD）设备。 ESD器件包括邻近绝缘区域的顶表面并且超过绝缘区域的顶表面的半导体鳍片。 ESD装置被配置为响应于第一节点上的ESD瞬变，将电流从第一节点传导到第二节点。

公开(公告)号：US08692290B2

公开(公告)日：2014-04-08

申请号：US13226838

申请日：2011-09-07

申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

IPC分类号： H01L29/73 ,  H01L21/331 ,  G06F17/50

CPC分类号： H01L29/66363 ,  G06F17/50 ,  H01L27/0262 ,  H01L29/74 ,  H01L29/7436 ,  H02H9/04

摘要： Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

摘要翻译： 可控硅整流器的器件结构和设计结构，以及制造可控硅整流器的方法。 器件结构包括设置在包含可控硅整流器的第一和第二p-n结的器件区域的顶表面上的不同材料的第一和第二层。 第一层横向定位在与第一p-n结垂直对准的顶表面上。 第二层横向定位在与第二p-n结垂直对准的器件区域的顶表面上。 包括第二层的材料具有比包含第一层的材料更高的电阻率。

公开(公告)号：US20130221433A1

公开(公告)日：2013-08-29

申请号：US13860371

申请日：2013-04-10

申请人： IO SEMICONDUCTOR, INC.

发明人： Stuart B. Molin ,  Michael A. Stuber

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L27/0823 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/1148 ,  H01L2224/1302 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/48 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/00

摘要： A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

摘要翻译： 在具有第一表面，第二表面和背景掺杂的半导体层中形成垂直半导体器件。 在半导体层的第二表面形成掺杂到与背景相反的导电类型的第一掺杂区域。 在第一掺杂区域的内部，在半导体层的第二表面形成与背景相同导电类型的第二掺杂区域。 半导体层的一部分在第一表面被去除，暴露出新的第三表面。 第三掺杂区域形成在第三表面的半导体层的内部。 至少对第二掺杂区域（经由第二表面）和第三掺杂区域（经由新的第三表面）进行电接触。 以这种方式，可以在减薄的半导体或SOI层中制造垂直DMOS，IGBT，双极晶体管，晶闸管和其他类型的器件。

公开(公告)号：US20130119522A1

公开(公告)日：2013-05-16

申请号：US13709786

申请日：2012-12-10

申请人： Infineon Technologies AG

发明人： Gerhard Schmidt ,  Hans-Joachim Schulze ,  Bernd Kolbesen

IPC分类号： H01L29/06

CPC分类号： H01L29/0607 ,  H01L21/223 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1016 ,  H01L29/167 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66909 ,  H01L29/7397 ,  H01L29/7802

摘要： A semiconductor substrate includes a first side and a second side opposite the first side. A semiconductor material extends between the first and second sides and is devoid of active device regions. The semiconductor material has a first region and a second region. The first region extends from the first side to a depth into the semiconductor material and includes chalcogen dopant atoms which provide a base doping concentration for the first region. The second region extends from the first region to the second side and is devoid of base doping. Further, a power semiconductor component is provided.

摘要翻译： 半导体衬底包括与第一侧相对的第一侧和第二侧。 半导体材料在第一和第二侧之间延伸并且没有有源器件区域。 半导体材料具有第一区域和第二区域。 第一区域从第一侧向深度延伸到半导体材料中，并且包括提供第一区域的基极掺杂浓度的硫族化合物掺杂剂原子。 第二区域从第一区域延伸到第二侧并且没有基底掺杂。 此外，提供功率半导体部件。

公开(公告)号：US20120018738A1

公开(公告)日：2012-01-26

申请号：US12843113

申请日：2010-07-26

申请人： Qingchun Zhang ,  Anant Agarwal

发明人： Qingchun Zhang ,  Anant Agarwal

IPC分类号： H01L29/24 ,  H01L29/744 ,  H01L29/74 ,  H01L29/72 ,  H01L21/332 ,  H01L21/331

CPC分类号： H01L29/66378 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66234 ,  H01L29/66363 ,  H01L29/744

摘要： Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.

摘要翻译： 公开了包括用于表面钝化的半导体凸缘层的电子器件结构及其制造方法。 在一个实施例中，电子器件包括具有交替掺杂类型的期望半导体材料的多个半导体层。 半导体层包括第一掺杂类型的基极层，其包括形成电子器件的第一接触区域的高度掺杂的阱和在基底层上的第二掺杂类型的一个或多个接触层，其被蚀刻以形成第二掺杂阱 电子设备的接触区域。 一个或多个接触层的蚀刻在基层的表面上引起显着的晶体损伤，并因此导致界面电荷。 为了钝化基底层的表面，半导体材料的半导体凸缘层至少在基底层的表面上外延生长。