公开(公告)号：US11997847B2

公开(公告)日：2024-05-28

申请号：US17588938

申请日：2022-01-31

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Shriram Shivaraman ,  Yih Wang ,  Tahir Ghani ,  Jack T. Kavalieros

IPC分类号： H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC分类号： H10B12/30 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78669 ,  H01L29/78693 ,  H10B12/05

摘要： Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US11996321B2

公开(公告)日：2024-05-28

申请号：US17350974

申请日：2021-06-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Chih Hsiung ,  Jyun-De Wu ,  Yi-Chun Chang ,  Yi-Chen Wang ,  Yuan-Tien Tu

IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L21/76802 ,  H01L21/76877 ,  H01L29/41733 ,  H01L29/42392

摘要： A method includes forming a conductive feature through a first dielectric layer, sequentially forming a second dielectric layer and a third dielectric layer over the first dielectric layer, and etching the third dielectric layer to form an opening. A first width of the opening at a top surface of the third dielectric layer is greater than a second width of the opening at a first interface between the third dielectric layer and the second dielectric layer. The method also includes etching the second dielectric layer until the opening extends to the conductive feature, thereby forming an enlarged opening, and forming a metal material in the enlarged opening. A third width of the enlarged opening at the first interface is equal to or less than a fourth width of the enlarged opening at a second interface between the second dielectric layer and the first dielectric layer.

公开(公告)号：US20240170370A1

公开(公告)日：2024-05-23

申请号：US18218615

申请日：2023-07-06

申请人： Samsung Electronics Co., Ltd.

发明人： Jina Lee ,  Jongdoo Kim ,  Bongkeun Kim

IPC分类号： H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： An integrated circuit device includes a first cell and a second cell apart from each other in a first lateral direction on a substrate, the first cell and the second cell each including a plurality of gate lines, an inter-cell isolation region between the first cell and the second cell, the inter-cell isolation region extending in a second lateral direction, a power line including portions overlapping a cell boundary of each of the first cell and the second cell in a vertical direction and a portion overlapping the inter-cell isolation region in the vertical direction, a plurality of dummy gate insulation lines, a bridge insulating pattern in contact with an end portion of each of the plurality of dummy gate insulation lines, and a via power rail passing through the bridge insulating pattern, the via power rail being connected to the power line.

公开(公告)号：US20240162228A1

公开(公告)日：2024-05-16

申请号：US18219875

申请日：2023-07-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Dongkyu LEE ,  Hyungjoo NA ,  Jinchan YUN ,  Cheoljin YUN ,  Kyuman HWANG

IPC分类号： H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

摘要： A three-dimensional semiconductor device includes a lower connection structure; a device structure; and an upper connection structure sequentially disposed along a first direction, wherein the device structure includes a substrate on the lower connection structure; first and second source/drain patterns on the substrate; a separation pattern adjacent in a second direction to the source/drain patterns, the second direction being parallel to a bottom surface of the substrate; and a through conductive pattern adjacent in a third direction to the separation pattern, the third direction being parallel to the bottom surface of the substrate and intersecting the second direction, the through conductive pattern connects the lower connection structure and the upper connection structure to each other, and the through conductive pattern is connected either through the lower connection structure to the first source/drain pattern or through the upper connection structure to the second source/drain pattern.

公开(公告)号：US20240155872A1

公开(公告)日：2024-05-09

申请号：US18281247

申请日：2022-09-22

申请人： Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

发明人： Yu Wang ,  Cong Fan ,  Xiangdan Dong ,  Donghui Tian

IPC分类号： H10K59/121 ,  H01L29/417 ,  H01L29/786 ,  H10K59/12 ,  H10K71/60

CPC分类号： H10K59/1213 ,  H01L29/41733 ,  H01L29/78645 ,  H10K59/1201 ,  H10K59/1216 ,  H10K71/60

摘要： A display substrate and a preparation method therefor, and a display device. The display substrate includes a display area, a blocking area, an opening area, and a base substrate. The blocking area includes at least one blocking wall at least partially surrounding the opening area. Each blocking wall includes a first metal layer structure and a first stack structure, and at least one side surface of the first metal layer structure surrounding the opening area (301) includes a first notch. The display area includes a plurality of sub-pixels, each sub-pixel includes a pixel driving circuit and a light-emitting device, the pixel driving circuit includes a thin-film transistor and a connector electrode, and the thin-film transistor includes a first source/drain electrode and a second source/drain electrode. The light-emitting device includes a first electrode a second electrode, and a light-emitting material layer between the first electrode and the second electrode.

公开(公告)号：US20240153990A1

公开(公告)日：2024-05-09

申请号：US18053795

申请日：2022-11-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Chanro Park ,  Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Juntao Li

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L23/48 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/481 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a source or drain (S/D) region. The FET also includes a backside S/D contact connected to a top surface of the S/D region. The backside S/D contact includes a lateral portion upon the top surface of the S/D region. The lateral portion further laterally extends adjacent to or past the first S/D region. The backside S/D contact includes a vertical portion that extends vertically downward from the lateral portion below the bottom surface of the substrate layer. The FET also includes a backside S/D mushroom that extends vertically downward from the vertical portion.

公开(公告)号：US20240153875A1

公开(公告)日：2024-05-09

申请号：US18054133

申请日：2022-11-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruilong Xie ,  Koichi Motoyama ,  Chih-Chao Yang ,  Feng Liu

IPC分类号： H01L23/528 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L21/28141 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0694 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78642

摘要： A semiconductor device includes a first source/drain element on a first side of the semiconductor device, a second source/drain element on an opposing side of the semiconductor device, a backside contact including a first contact end on a first end of the first source/drain element and an opposing contact end in electrical communication with a backside power distribution network, a critical dimension of the first contact end is smaller than the critical dimension of the opposing contact end, and the backside contact is substantially aligned to the first source/drain element. The semiconductor device also includes and a source/drain placeholder material with a critical dimension of a middle portion of the source/drain placeholder material being larger than the critical dimension of both tend portions.

公开(公告)号：US20240153874A1

公开(公告)日：2024-05-09

申请号：US18159773

申请日：2023-01-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Ju Chen ,  Chung-Ting Li

IPC分类号： H01L23/528 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/522 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

CPC分类号： H01L23/5283 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5226 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H10B10/125

摘要： A semiconductor device includes a forksheet structure extending lengthwise along a first direction over a substrate. The forksheet structure has a dielectric wall separating a stack of n-type nanostructures from a stack of p-type nanostructures. A gate structure is over the forksheet structure, the gate structure extending lengthwise along a second direction perpendicular to the first direction. The gate structure is in direct contact with the stack of n-type and p-type nanostructures and in direct contact with the dielectric wall. A first gate interconnect is over and in direct contact with the gate structure and a first gate via is over and in direct contact with the first gate interconnect.

公开(公告)号：US11978804B2

公开(公告)日：2024-05-07

申请号：US17496690

申请日：2021-10-07

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Yih Wang

IPC分类号： H01L29/786 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H10B12/00

CPC分类号： H01L29/78618 ,  H01L23/528 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78684 ,  H01L29/7869 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

摘要： A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

公开(公告)号：US20240145561A1

公开(公告)日：2024-05-02

申请号：US18409119

申请日：2024-01-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ting TSAI ,  Chung-Liang CHENG ,  Hong-Ming LO ,  Chun-Chih LIN ,  Chyi-Tsong NI

IPC分类号： H01L29/417 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L29/41775 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908

摘要： A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.