公开(公告)号：US20250093763A1

公开(公告)日：2025-03-20

申请号：US18818984

申请日：2024-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Akio Misaka ,  Bongkeun Kim ,  Ran Lee ,  Sanghwa Lee ,  Wonjoo Im

IPC: G03F1/24 ,  G03F7/00

Abstract: A photomask for a photolithography process includes a mask substrate, a reflective multilayer on the mask substrate, and a light absorber pattern on the reflective multilayer and having hole patterns, wherein the hole patterns include a main hole pattern for pattern transfer onto a wafer, first sub-resolution assist feature (SRAF) hole patterns arranged at regular intervals to provide honeycomb lattices in a first region centered around the main hole pattern and having a first pitch less than or equal to a diffraction limit in the photolithography process, and second SRAF hole patterns arranged at regular intervals to surround the main hole pattern and the first SRAF patterns and providing honeycomb lattices in a second region centered around the main hole pattern and surrounding the first region, the second SRAF hole patterns being arranged with a second pitch less than or equal to the diffraction limit in the photolithography process.

公开(公告)号：US20250036022A1

公开(公告)日：2025-01-30

申请号：US18632558

申请日：2024-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghwa Woo ,  Wooseok Kim ,  Bongkeun Kim ,  Sanghwa Lee

IPC: G03F1/36

Abstract: Provided is an optical proximity correction (OPC) method including receiving a design layout for a target pattern to be formed on a substrate, obtaining a first OPC pattern by performing a baseline OPC on the design layout, and obtaining a second OPC pattern by curving the first OPC pattern.

公开(公告)号：US20240170370A1

公开(公告)日：2024-05-23

申请号：US18218615

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jina Lee ,  Jongdoo Kim ,  Bongkeun Kim

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a first cell and a second cell apart from each other in a first lateral direction on a substrate, the first cell and the second cell each including a plurality of gate lines, an inter-cell isolation region between the first cell and the second cell, the inter-cell isolation region extending in a second lateral direction, a power line including portions overlapping a cell boundary of each of the first cell and the second cell in a vertical direction and a portion overlapping the inter-cell isolation region in the vertical direction, a plurality of dummy gate insulation lines, a bridge insulating pattern in contact with an end portion of each of the plurality of dummy gate insulation lines, and a via power rail passing through the bridge insulating pattern, the via power rail being connected to the power line.

公开(公告)号：US20240104287A1

公开(公告)日：2024-03-28

申请号：US18370921

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dawoon Choi ,  Inseop Lee ,  Hee Jeong ,  Bongkeun Kim ,  Myungsoo Noh

IPC: G06F30/398 ,  G03F1/36 ,  G06F30/392

CPC classification number: G06F30/398 ,  G03F1/36 ,  G06F30/392

Abstract: Provided is a layout design method including designing a preliminary layout including a source/drain contact pattern of an integrated circuit device, designing a first layout including a cut pattern for cutting the source/drain contact pattern, designing a second layout configured by excluding a pattern overlapping the pattern of the first layout from the preliminary layout, and correcting the preliminary layout by reflecting an etch skew based on at least one parameter of the second layout.

公开(公告)号：US20240339379A1

公开(公告)日：2024-10-10

申请号：US18511607

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Da Woon Choi ,  Bongkeun Kim ,  Myung Soo Noh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a substrate, a first active pattern extending in a first horizontal direction, a second active pattern extending in the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction, a gate electrode extending in the second horizontal direction, a source/drain region disposed on a side of the gate electrode, a first through-via disposed inside the substrate between the first and second active patterns, an upper interlayer insulating layer covering the source/drain region, and a second through-via connected to the first through-via by passing through the upper interlayer insulating layer in a vertical direction spaced apart from the source/drain region in the second horizontal direction. A width of the first through-via in the second horizontal direction is continuously reduced as the first through-via becomes adjacent to the lower surface of the substrate.