公开(公告)号：US20230135975A1

公开(公告)日：2023-05-04

申请号：US17966182

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Jeong ,  Noyoung Chung ,  Inseop Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/49 ,  H01L29/775 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure extending in a second direction intersecting the active region on the substrate and including a gate dielectric layer and a gate electrode, channel layers spaced apart from each other in a third direction perpendicular to an upper surface of the substrate on the active region and surrounded by the gate structure, a lateral structure disposed on internal side surfaces of the gate dielectric layer and contacting the gate dielectric layer and the gate electrode, and source/drain regions disposed in regions in which the active region is recessed on opposite sides of the gate structure, and connected to the channel layers. A level of lower surfaces of the lateral structures is higher than a level of a lower surface of the gate electrode.

公开(公告)号：US20240104287A1

公开(公告)日：2024-03-28

申请号：US18370921

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dawoon Choi ,  Inseop Lee ,  Hee Jeong ,  Bongkeun Kim ,  Myungsoo Noh

IPC: G06F30/398 ,  G03F1/36 ,  G06F30/392

CPC classification number: G06F30/398 ,  G03F1/36 ,  G06F30/392

Abstract: Provided is a layout design method including designing a preliminary layout including a source/drain contact pattern of an integrated circuit device, designing a first layout including a cut pattern for cutting the source/drain contact pattern, designing a second layout configured by excluding a pattern overlapping the pattern of the first layout from the preliminary layout, and correcting the preliminary layout by reflecting an etch skew based on at least one parameter of the second layout.