公开(公告)号：US20230071777A1

公开(公告)日：2023-03-09

申请号：US17739752

申请日：2022-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjoo Im ,  Noyoung Chung ,  Sanghwa Lee

IPC: G03F7/20 ,  G03F1/36

Abstract: A method of manufacturing a semiconductor chip includes designing a layout for a semiconductor chip, performing an optical proximity correction (OPC) on the layout, manufacturing a mask after performing the OPC, and manufacturing the semiconductor chip using the mask, wherein a plurality of OPC shapes corresponding to a rectangular pattern of the mask are included in the mask and at least one of the plurality of OPC shapes includes a multi-edge corner rounding OPC shape.

公开(公告)号：US12159832B2

公开(公告)日：2024-12-03

申请号：US17648598

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dawoon Choi ,  Myungsoo Noh ,  Noyoung Chung ,  Sunghun Jung

IPC: H01L29/786 ,  B82Y10/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a device region of a substrate. A gate line extends in a second lateral direction on the fin-type active region. The second lateral direction intersects with the first lateral direction. A source/drain region is adjacent to one side of the gate line on the fin-type active region. A gate contact is on the gate line and connected to the gate line. A source/drain contact is on the source/drain region and includes a first segment facing the gate contact and a second segment integrally connected to the first segment. The second segment extends from the first segment in the second lateral direction. In the first lateral direction, a first distance from the first segment to the gate line is greater than a second distance from the second segment to the gate line.

公开(公告)号：US20230205963A1

公开(公告)日：2023-06-29

申请号：US17961710

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Akio Misaka ,  Noyoung Chung ,  Taekyum Kim ,  Sanghwa Lee ,  Woonhyuk Choi

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: A layout method of a semiconductor chip, includes designing a layout using a restriction rule such that a layout pattern having a length smaller than a first length in a first direction has to have a length smaller than a second length in a second direction, the second direction intersecting the first direction, generating a plurality of unit regions by partitioning the layout in the first direction, generating a plurality of target regions by adding a reference region to a partitioned edge of each of the plurality of unit regions, retargeting the plurality of target regions in parallel, and generating a correction layout by merging the plurality of retargeted target regions.

公开(公告)号：US20220216150A1

公开(公告)日：2022-07-07

申请号：US17409069

申请日：2021-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongchan Shin ,  Woojeong Shin ,  Changmin Park ,  Noyoung Chung

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a logic cell on a substrate and a first metal layer on the logic cell. The first metal layer includes first and second power lines that extend in a first direction, and first, second, and third lower interconnection lines, which are respectively disposed on first, second, and third interconnection tracks defined between the first and second power lines that extend in the first direction parallel to each other. The first lower interconnection line includes first and second interconnection lines spaced apart from each other by a first distance, and the third lower interconnection line includes third and fourth interconnection lines spaced apart from each other by a second distance. The first and third interconnection lines have first and second ends, respectively, which face the second and fourth interconnection lines, respectively, and have different curvatures.

公开(公告)号：US11733604B2

公开(公告)日：2023-08-22

申请号：US17236440

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeong Seop Kim ,  Noyoung Chung

IPC: G03F1/36 ,  H01L21/027 ,  H01L21/285 ,  G06F30/392 ,  H01L21/8238

CPC classification number: G03F1/36 ,  G06F30/392 ,  H01L21/0274 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes performing an optical proximity correction (OPC) on design patterns of a layout to generate a corrected layout, and forming a photoresist pattern on a substrate using a photomask manufactured based on the corrected layout. The OPC comprises generating develop targets for the design patterns, respectively, choosing first object patterns based on distances between the develop targets, performing a first OPC operation on the design patterns based on a mask rule to generate first correction patterns, choosing second object patterns by considering distances between the first correction patterns and a target error of each of the first correction patterns, and performing a second OPC operation on the first and second object patterns to generate second correction patterns, the performing the second OPC not based on the mask rule.

公开(公告)号：US20210063868A1

公开(公告)日：2021-03-04

申请号：US16939828

申请日：2020-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narae Bang ,  Sang-Hwa Lee ,  Noyoung Chung

IPC: G03F1/36 ,  G03F7/20 ,  H01L21/033

Abstract: Disclosed are mask layout correction methods and a method for fabricating semiconductor devices. The mask layout correction method comprises performing a first optical proximity correction on an initial pattern layout. The step of performing the first optical proximity correction includes providing a target pattern of the initial pattern layout with control points based on a first model, obtaining a predicted contour of the initial pattern layout by performing a simulation, and obtaining an error between the target pattern and the predicted contour from the control points. The control points include first control points on an edge of the target pattern and second control points in an inside of the target pattern. The step of obtaining the error includes acquiring first error values from the first control points, providing weights to the first error values, and acquiring second error values from the second control points.

公开(公告)号：US09996658B2

公开(公告)日：2018-06-12

申请号：US15433835

申请日：2017-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngseok Kim ,  Noyoung Chung

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: A method for manufacturing a semiconductor device includes obtaining a design layout for a target layer of an optical proximity correction process, the design layout including a first block and a second block being a repetition block of the first block, dividing the design layout into a plurality of patches, performing the optical proximity correction process on the patches of the first block, applying corrected patches of the first block to the patches of the second block, respectively, forming a correction layout by performing the optical proximity correction process on boundary patches of the second block, fabricating a photomask corresponding to the correction layout, and forming patterns on a substrate corresponding to the photomask. Each of the patches is a standard unit on which the optical proximity correction process is performed.

公开(公告)号：US12299368B2

公开(公告)日：2025-05-13

申请号：US17554517

申请日：2021-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Akio Misaka ,  Jongdoo Kim ,  Noyoung Chung

IPC: G06F30/392 ,  G03F7/00 ,  G06F30/398 ,  G06F119/18 ,  H01L27/02

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes generating a first virtual layout by placing and routing standard cells using a virtual netlist, searching first duplicate pattern regions in the first virtual layout and choosing one of them as a first representative pattern region, performing an OPC operation on the first representative pattern region to obtain a first OPC result, generating an actual layout by placing and routing standard cells using an actual netlist, performing an OPC operation on the actual layout, and forming a photoresist pattern on a substrate using a photomask manufactured based on the actual layout, to which the OPC operation is applied.

公开(公告)号：US11698581B2

公开(公告)日：2023-07-11

申请号：US17360365

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Akio Misaka ,  Changsoo Kim ,  Noyoung Chung

IPC: G03F1/36 ,  G06F30/392 ,  G06N20/00

CPC classification number: G03F1/36 ,  G06F30/392 ,  G06N20/00

Abstract: A non-transitory computer-readable medium storing codes that, when executed by a processor, cause the processor to perform operations of receiving full chip data including specific patterns of a first layout, extracting a representative pattern of the first layout from the full chip data, generating a vector of the extracted representative pattern, generating a first data set based on the generated vector, generating a machine learning model by performing machine learning with respect to the first data set, executing an optical proximity correction (OPC) with respect to the specific patterns of the first layout by using the machine learning model, and generating a second layout based on a result of executing the OPC may be provided.

公开(公告)号：US20230135975A1

公开(公告)日：2023-05-04

申请号：US17966182

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Jeong ,  Noyoung Chung ,  Inseop Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/49 ,  H01L29/775 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure extending in a second direction intersecting the active region on the substrate and including a gate dielectric layer and a gate electrode, channel layers spaced apart from each other in a third direction perpendicular to an upper surface of the substrate on the active region and surrounded by the gate structure, a lateral structure disposed on internal side surfaces of the gate dielectric layer and contacting the gate dielectric layer and the gate electrode, and source/drain regions disposed in regions in which the active region is recessed on opposite sides of the gate structure, and connected to the channel layers. A level of lower surfaces of the lateral structures is higher than a level of a lower surface of the gate electrode.