公开(公告)号：US09495518B2

公开(公告)日：2016-11-15

申请号：US13407333

申请日：2012-02-28

Applicant: Yong June Kim ,  Hong Rak Son ,  Jae Hong Kim ,  Sang Yong Yoon ,  Ki Jun Lee ,  Jung Soo Chung ,  Seong Hyeog Choi

Inventor： Yong June Kim ,  Hong Rak Son ,  Jae Hong Kim ,  Sang Yong Yoon ,  Ki Jun Lee ,  Jung Soo Chung ,  Seong Hyeog Choi

IPC: G06F12/00 ,  G06F21/00 ,  G06F12/14 ,  G11C11/00 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  G06F11/10

CPC classification number: G06F21/00 ,  G06F11/1012 ,  G06F11/108 ,  G06F12/00 ,  G06F12/14 ,  G11C11/00 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418

Abstract: An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.

Abstract translation: 一种用于从非易失性存储器读取的装置和方法，由此使用软判决数据来确定硬判决数据的可靠性。 从非易失性存储器读取的硬判决数据被去随机化，并且从非易失性存储器读取的软判决数据不被去随机化。 使用软判决数据，硬判决数据被解码。

公开(公告)号：US09378798B2

公开(公告)日：2016-06-28

申请号：US14970563

申请日：2015-12-16

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Abstract translation: 自旋转矩磁阻存储器包括耦合到磁头阵列的阵列读取电路和阵列写入电路。 阵列读取电路对阵列中的磁头进行采样，向磁头施加写入电流脉冲以将其设置为第一逻辑状态，对磁头进行重新采样，并比较采样和重采样的结果，以确定每个磁性的位状态 位。 对于具有第二逻辑状态的页面中的每个磁性位，阵列写入电路启动回写，其中写回包括施加与第一写入电流脉冲相比具有相反极性的第二写入电流脉冲以设置 磁头到第二个状态。 在写回开始之后可以接收读取或写入操作，其中在写入操作的情况下可以中止一部分位的写回。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。 在重采样期间也可以使用偏移电流。

公开(公告)号：US20160094224A1

公开(公告)日：2016-03-31

申请号：US14864339

申请日：2015-09-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: H03K19/00

CPC classification number: H03K19/0013 ,  G09G3/20 ,  G11C7/1006 ,  G11C7/12 ,  G11C11/00 ,  G11C11/401 ,  G11C11/4094 ,  H01L27/10814 ,  H03K19/0966

Abstract: A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor.

Abstract translation: 提高了动态逻辑电路的驱动能力。 逻辑电路包括动态逻辑电路，第一输出节点，二极管连接的第一晶体管和电容器。 动态逻辑电路包括第二输出节点。 动态逻辑电路中的第一晶体管和晶体管具有n型导电性或p型导电性。 第一输出节点电连接到电容器的第一端子，并且第二输出节点电连接到电容器的第二端子。 第一晶体管的第一端子电连接到第一输出节点，并且第一电压被输入到第一晶体管的第二端子。

公开(公告)号：US20160049194A1

公开(公告)日：2016-02-18

申请号：US14458813

申请日：2014-08-13

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/00 ,  G11C11/1677 ,  G11C13/0064 ,  G11C2013/0066

Abstract: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a programming signal to a memory cell in the array, the programming signal associated with programming the memory cell to a particular data state; and determine, via an integration component, if a data state of the memory cell changes to a different data state responsive to the programming signal being provided.

Abstract translation: 本公开包括用于感测电阻变量存储单元的装置和方法。 许多实施例包括向阵列中的存储器单元提供编程信号的电路，与将存储器单元编程为特定数据状态相关联的编程信号; 并且通过积分分量确定响应于所提供的编程信号，存储器单元的数据状态是否变为不同的数据状态。

公开(公告)号：US20150348644A1

公开(公告)日：2015-12-03

申请号：US14823033

申请日：2015-08-11

Applicant: Apple Inc.

Inventor： Ronen Dar

IPC: G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G06F11/1048 ,  G06F11/1068 ,  G06F12/0246 ,  G11C11/00 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3422 ,  G11C16/3431 ,  G11C29/52

Abstract: A method includes storing data in a memory that includes multiple analog memory cells. After storing the data, an interference caused by a first group of the analog memory cells to a second group of the analog memory cells is estimated. The data stored in the first group is reconstructed based on the estimated interference caused by the first group to the second group.

Abstract translation: 一种方法包括将数据存储在包括多个模拟存储器单元的存储器中。 在存储数据之后，估计由第一组模拟存储单元引起的对第二组模拟存储单元的干扰。 基于由第一组到第二组引起的估计干扰来重构存储在第一组中的数据。

公开(公告)号：US09190133B2

公开(公告)日：2015-11-17

申请号：US13793347

申请日：2013-03-11

Applicant: Micron Technology, Inc.

Inventor： Dean K. Nobunaga ,  Ali Feiz Zarrin Ghalam ,  Xiaojiang Guo ,  Eric N. Lee

IPC: G06F12/00 ,  G11C11/00 ,  G06F12/08

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0893 ,  G06F13/1684 ,  G06F13/4068 ,  G06F2212/1016 ,  G06F2212/3042 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C11/00

Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.

Abstract translation: 本文公开了用于减小数据总线上的电容的装置和方法。 根据一个或多个所描述的实施例，装置可以包括耦合到内部数据总线和命令和地址总线的多个存储器，每个存储器被配置为在命令和地址总线上接收命令。 多个存储器中的一个可以耦合到外部数据总线。 多个存储器中的一个可以被配置为当命令包括程序命令时向内部数据总线提供程序数据，并且多个存储器中的另一个是程序命令的目标存储器，并且可以被配置为将读取数据提供给 当命令包括读取命令并且多个存储器中的另一个是读取命令的目标存储器时的外部数据总线。

公开(公告)号：US20150213882A1

公开(公告)日：2015-07-30

申请号：US14679110

申请日：2015-04-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro OHMARU

IPC: G11C11/419 ,  G11C11/412 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/00 ,  G11C11/412

Abstract: To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.

Abstract translation: 为了降低功耗，存储电路包括：锁存单元，其中根据控制信号重写和读取第一数据和第二数据;第一开关单元，其通过以下步骤控制对存储在锁存单元中的第一数据的重写和读取： 响应于所述控制信号而导通或断开;以及第二开关单元，其响应于所述控制信号而导通或关断控制存储在所述锁存单元中的所述第二数据的重写和读取。 闩锁单元包括第一反相器和第二反相器。 第一反相器和第二反相器中的至少一个包括第一场效应晶体管和第二场效应晶体管，其具有与第一场效应晶体管相同的导电类型，并且具有根据控制的栅极电位 信号。

公开(公告)号：US09093139B2

公开(公告)日：2015-07-28

申请号：US13442829

申请日：2012-04-09

Applicant: Jannier Maximo Roiz Wilson

Inventor： Jannier Maximo Roiz Wilson

IPC: G11C11/00

CPC classification number: G11C11/00 ,  G11C11/15

Abstract: A magnetic memory cell is provided. The cell comprises first and second free layers; and an intermediate layer separating the first and second free layers, wherein the first and second free layers are magnetostatically coupled.

Abstract translation: 提供磁存储单元。 该电池包括第一和第二自由层; 以及分离第一和第二自由层的中间层，其中第一和第二自由层被静磁耦合。

公开(公告)号：US20150194210A1

公开(公告)日：2015-07-09

申请号：US14666360

申请日：2015-03-24

Applicant: Kabushiki Kaisha Toshiba

Inventor： Shigeki KOBAYASHI ,  Takeshi YAMAGUCHI

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/22 ,  G11C11/00 ,  G11C13/0004 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/71 ,  G11C2213/72

Abstract: A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.

Abstract translation: 根据实施例的半导体存储器件包括：控制电路，被配置为将第一电压施加到所选择的第一线，向所选择的第二线施加第二电压，并将第三电压和第四电压施加到未选择的第一线 和设置操作中的未选择的第二行。 控制电路包括检测电路，其被配置为使用参考电压来检测所选存储单元的电阻状态的转变。 控制电路被配置为执行读取操作，其中控制电路将第三电压施加到所选择的第一行和未选择的第一行，将第二电压施加到所选择的第二行，并将第四电压施加到非选择的第二行， - 选择的第二行，并且基于所选择的第二行的电压值设置参考电压。

公开(公告)号：US20150179924A1

公开(公告)日：2015-06-25

申请号：US14639259

申请日：2015-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sergiy ROMANOVSKYY

IPC: H01L43/08 ,  G11C13/00 ,  H01L43/02

CPC classification number: H01L43/08 ,  G11C11/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C13/004 ,  G11C13/0069 ,  H01L43/02

Abstract: A magnetoresistive random access memory (MRAM) bit cell includes a first magnetic tunnel junction (MTJ) connected to a first data line. The MRAM bit cell further includes a second MTJ connected to a second data line. The MRAM bit cell further includes a pass gate assembly connected to the first MTJ and the second MTJ, wherein the pass gate assembly comprises a plurality of transistors, and each transistor of the plurality of transistors is configured to selectively connect the first MTJ and the second MTJ to a driving line.

Abstract translation: 磁阻随机存取存储器（MRAM）位单元包括连接到第一数据线的第一磁性隧道结（MTJ）。 MRAM位单元还包括连接到第二数据线的第二MTJ。 所述MRAM位单元还包括连接到所述第一MTJ和所述第二MTJ的通孔组件，其中所述通道组件包括多个晶体管，并且所述多个晶体管中的每个晶体管被配置为选择性地连接所述第一MTJ和所述第二MTJ MTJ到行车线。