公开(公告)号：US20220037251A1

公开(公告)日：2022-02-03

申请号：US17198591

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US20210082799A1

公开(公告)日：2021-03-18

申请号：US16879009

申请日：2020-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  H01L21/768 ,  H01L29/423 ,  H01L27/108 ,  G11C5/10

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US10714478B2

公开(公告)日：2020-07-14

申请号：US16532857

申请日：2019-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

公开(公告)号：US10685963B2

公开(公告)日：2020-06-16

申请号：US16242127

申请日：2019-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Keunnam Kim ,  Eun A Kim ,  Eunjung Kim ,  Jeongseop Shim

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure across the active patterns and extending in a first direction, forming a first mask pattern on the active structure, and forming a trench by using the first mask pattern as an etching mask to pattern the active structure. Forming the first mask pattern comprises forming in a first mask layer a plurality of first openings extending in a second direction intersecting the first direction, and forming in the first mask layer a plurality of second openings extending in a third direction intersecting the first and second directions.

公开(公告)号：US10600791B2

公开(公告)日：2020-03-24

申请号：US16125167

申请日：2018-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Wan Kim ,  Keunnam Kim ,  Juik Lee

IPC: H01L27/108 ,  H01L27/22 ,  G11C8/08 ,  H01L23/535 ,  H01L27/24 ,  G11C8/14

Abstract: A semiconductor memory device includes a word line buried in an upper portion of a substrate and extending in a first direction, and a word line contact plug connected to the word line. An end portion of the word line includes a contact surface exposed in the first direction, and the word line contact plug is connected to the contact surface.

公开(公告)号：US20180040560A1

公开(公告)日：2018-02-08

申请号：US15592860

申请日：2017-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/2436 ,  H01L27/2463

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US09607994B2

公开(公告)日：2017-03-28

申请号：US14755690

申请日：2015-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunnam Kim ,  Sunyoung Park ,  Kyehee Yeom ,  Hyeon-Woo Jang ,  Jin-Won Jeong ,  Changhyun Cho ,  HyeongSun Hong

IPC: H01L27/108 ,  H01L21/265 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/26513 ,  H01L21/7682 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.