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    Memory device and operation method thereof
    61.
    发明授权
    Memory device and operation method thereof 有权

    公开(公告)号：US12119063B2

    公开(公告)日：2024-10-15

    申请号：US17957532

    申请日：2022-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Wan Nam ,  Hyunggon Kim ,  Bong-Kil Jung ,  Younho Hong ,  Juseong Hwang

    IPC: G11C16/08

    CPC classification number: G11C16/08

    Abstract: Disclosed is a memory device includes a memory block that is connected with a plurality of wordlines, a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines, and an address decoding circuit configured to connect the plurality of driving lines with unselected wordlines of the plurality of wordlines. During a wordline setup period for the plurality of wordlines, the voltage generating circuit floats first driving lines corresponding to first unselected wordlines of the unselected wordlines from among the plurality of driving lines when the first unselected wordlines reach a first target level, and floats second driving lines corresponding to second unselected wordlines of the unselected wordlines from among the plurality of driving lines when the second unselected wordlines reach a second target level different from the first target level.

    Nonvolatile memory device
    64.
    发明授权
    Nonvolatile memory device 有权

    公开(公告)号：US11238934B2

    公开(公告)日：2022-02-01

    申请号：US16991912

    申请日：2020-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Wan Nam ,  Euihyun Cheon ,  Byungjun Min

    IPC: G11C16/08 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/16 ,  G11C16/04

    Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region. The peripheral circuit region includes a block selecting circuit, a block unselecting circuit, and a first metal pad. The memory cell region is vertically connected to the peripheral circuit region, and includes a first memory block and a second metal pad directly connected to the first metal pad. The block selecting circuit is connected with ground selection lines, word lines, and string selection lines, and provides corresponding driving voltages to the ground selection lines, the word lines, and the string selection lines in response to a block selection signal corresponding to the first memory block, respectively. The block unselecting circuit is connected only with specific string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.

    Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same
    66.
    发明授权
    Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same 有权

    公开(公告)号：US11056194B2

    公开(公告)日：2021-07-06

    申请号：US17036387

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-Bo Shim ,  Sang-Wan Nam ,  Ji-Ho Cho

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C7/10 ,  G11C16/04 ,  G11C8/14

    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block. The control circuit receives a data erase command for a selected sub-block among the plurality of sub-blocks, performs a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, selectively performs a soft program operation on the at least one victim sub-block based on a result of the data read operation, and performs a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.

    Memory device including NAND strings and method of operating the same
    69.
    发明授权
    Memory device including NAND strings and method of operating the same 有权

    公开(公告)号：US10573386B2

    公开(公告)日：2020-02-25

    申请号：US16035958

    申请日：2018-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wan-Dong Kim ,  Tae-Hyun Kim ,  Sang-Wan Nam ,  Sang-Soo Park ,  Jae-Yong Jeong

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/28 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/32 ,  G11C5/06

    Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.

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