公开(公告)号：US20160126144A1

公开(公告)日：2016-05-05

申请号：US14991882

申请日：2016-01-08

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L21/823814 ,  C23C14/24 ,  C23C14/54 ,  C23C16/46 ,  C23C16/52 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66568

Abstract: A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.

公开(公告)号：US09257556B2

公开(公告)日：2016-02-09

申请号：US14269981

申请日：2014-05-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Vladimir Machkaoutsan ,  Kern Rim ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.

Abstract translation: 形成FinFET器件的半导体鳍片的方法包括在半导体鳍片上共形沉积硅 - 锗（SiGe）的非晶或多晶薄膜。 该方法还包括氧化非晶或多晶薄膜以将锗从非晶或多晶薄膜扩散到半导体鳍中。 这种方法还包括去除非晶或多晶薄膜的氧化部分。

公开(公告)号：US20220037493A1

公开(公告)日：2022-02-03

申请号：US16944624

申请日：2020-07-31

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/167

Abstract: Gate-all-around (GAA) transistors with shallow source/drain regions and methods of fabricating the same provide a GAA transistor that includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate and the source and drain regions, a filler material is provided adjacent the bottom gate, and the source and drain regions are grown on top of the filler material. In this fashion, the bottom gate does not abut the source region or the drain region, reducing geometries which would contribute to parasitic capacitance.

公开(公告)号：US11152347B2

公开(公告)日：2021-10-19

申请号：US15952638

申请日：2018-04-13

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  John Jianhong Zhu ,  Da Yang

IPC: H01L27/02 ,  H01L23/48 ,  H03K3/3562 ,  H01L27/118

Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

公开(公告)号：US11145654B2

公开(公告)日：2021-10-12

申请号：US16654774

申请日：2019-10-16

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong Lim ,  Stanley Seungchul Song ,  Jun Yuan ,  Kern Rim

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A device comprising a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, and a first gate surrounding the first plurality of channels. The first plurality of channels is located between the first source and the first drain. At least one channel includes silicon germanium (SiGe). The transistor is a field effect transistor (FET). The transistor is a gate all around (GAA) FET. The transistor may be configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor. The transistor may be configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.

公开(公告)号：US11121075B2

公开(公告)日：2021-09-14

申请号：US15933581

申请日：2018-03-23

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Kern Rim

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L23/532

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a signaling interconnect having a narrow trench disposed within a metallization layer, and a power rail having a wide trench disposed within the metallization layer, wherein the signaling interconnect comprises non-copper material and the power rail comprises copper. The non-copper material may include at least one of ruthenium (Ru), tungsten (W), aluminum (Al), and cobalt (Co). The signaling interconnect and power rail may be processed in a common chemical mechanical polishing step and have approximately the same trench depth. A metal cap may be deposited on top of the power rail.

公开(公告)号：US11038344B2

公开(公告)日：2021-06-15

申请号：US16362417

申请日：2019-03-22

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Xiangdong Chen ,  Haining Yang ,  Kern Rim

IPC: H02H9/04 ,  H02J7/00 ,  H01Q1/22

Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

公开(公告)号：US10854604B1

公开(公告)日：2020-12-01

申请号：US16578101

申请日：2019-09-20

Applicant: QUALCOMM Incorporated

Inventor： ChihWei Kuo ,  Haining Yang ,  Jun Yuan ,  Kern Rim

IPC: H01L27/092 ,  H03K19/0185 ,  H02M7/515

Abstract: Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.

公开(公告)号：US10763364B1

公开(公告)日：2020-09-01

申请号：US16895909

申请日：2020-06-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US10559501B2

公开(公告)日：2020-02-11

申请号：US15271043

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Song ,  Jeffrey Xu ,  Da Yang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L21/3065

Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.