公开(公告)号：US20200350124A1

公开(公告)日：2020-11-05

申请号：US16748775

申请日：2020-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Kai LIU

IPC: H01G4/30 ,  H01L49/02 ,  H01G4/33 ,  H01G4/012

Abstract: Planarization of the M1 metal layer reduces surface roughness and fills in pin-holes for a more reliable capacitor. For example, a MIM capacitor on a glass substrate may begin with patterning of the M1 layer, deposition of a planarization material, etch back the planarization material to planarize the M1 surface and fill in any pits/pin-holes. In addition, multiple-cycles of deposit and etch back further reduce M1 surface roughness and fill in possible pin-holes to acceptable level.

公开(公告)号：US20200259004A1

公开(公告)日：2020-08-13

申请号：US16274094

申请日：2019-02-12

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66 ,  H01L29/205

Abstract: Power amplifiers in radio frequency circuits are typically implemented as heterojunction bipolar transistors. In applications such as in 5G systems, the circuits are expected to operate at very high speeds, e.g., up to 100 GHz. Also, a certain amount of output power should be maintained for stable operation. To achieve both high power and high speed, it is proposed to incorporate field plates in the heterojunction bipolar transistors to reduce electric field in the collector. This allows the breakdown voltage of the transistor to be high, which aids in power output. At the same time, the collector can be relatively thin, which aids in operation speed.

公开(公告)号：US20200052103A1

公开(公告)日：2020-02-13

申请号：US16058388

申请日：2018-08-08

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

Abstract: Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer. The HEMT also includes a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer. The HEMT further includes n-doped protuberance(s) disposed above the AlGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.

公开(公告)号：US20190385947A1

公开(公告)日：2019-12-19

申请号：US16007921

申请日：2018-06-13

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Bin YANG ,  Gengming TAO

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/528 ,  H01L23/66

Abstract: A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.

公开(公告)号：US20190312153A1

公开(公告)日：2019-10-10

申请号：US15947667

申请日：2018-04-06

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

IPC: H01L29/93 ,  H01L27/08 ,  H01L29/06 ,  H01L29/94 ,  H01L29/739 ,  H01G7/06

Abstract: Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

公开(公告)号：US20190088765A1

公开(公告)日：2019-03-21

申请号：US16196384

申请日：2018-11-20

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI ,  Periannan CHIDAMBARAM

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/423 ,  H01L29/40 ,  H01L29/778 ,  H01L21/285 ,  H01L29/47 ,  H01L29/812 ,  H01L29/20

Abstract: A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.

公开(公告)号：US20190013398A1

公开(公告)日：2019-01-10

申请号：US15645188

申请日：2017-07-10

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO ,  Periannan CHIDAMBARAM

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L21/74 ,  H01L23/66

Abstract: A compound semiconductor field effect transistor may include a channel layer. The compound semiconductor transistor may also include a multi-layer epitaxial barrier layer on the channel layer. The channel layer may be on a doped buffer layer or on a first un-doped buffer layer. The compound semiconductor field effect transistor may further include a gate. The gate may be on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer.

公开(公告)号：US20180277657A1

公开(公告)日：2018-09-27

申请号：US15683530

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI ,  Periannan CHIDAMBARAM

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L21/768

CPC classification number: H01L29/66621 ,  H01L21/28581 ,  H01L21/28587 ,  H01L21/76822 ,  H01L29/20 ,  H01L29/402 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/475 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/8128

Abstract: A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.

公开(公告)号：US20180247933A1

公开(公告)日：2018-08-30

申请号：US15587837

申请日：2017-05-05

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/778 ,  H01L29/737 ,  H01L29/20 ,  H01L23/532 ,  H01L23/535 ,  H01L21/8252 ,  H01L21/768 ,  H01L23/66

CPC classification number: H01L27/0605 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76895 ,  H01L21/8252 ,  H01L23/5227 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/535 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/737 ,  H01L29/7786 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6677

Abstract: An integrated compound semiconductor circuit including a high-Q passive device may include a compound semiconductor transistor. The integrated compound semiconductor circuity may also include a high-Q inductor device. The integrated compound semiconductor may further include a back-end-of-line interconnect layer electrically contacting the high-Q inductor device and the compound semiconductor transistor, the back-end-of-line interconnect layer comprising a gold base layer and a copper interconnect layer.

公开(公告)号：US20180211897A1

公开(公告)日：2018-07-26

申请号：US15597386

申请日：2017-05-17

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI

IPC: H01L23/367 ,  H01L29/737 ,  H01L29/205 ,  H01L29/225 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L23/3677 ,  H01L29/0821 ,  H01L29/205 ,  H01L29/225 ,  H01L29/41708 ,  H01L29/66318 ,  H01L29/7371

Abstract: A heterojunction bipolar transistor may include an emitter, a base contacting the emitter, a collector contacting the base, a sub-collector contacting the collector, and an electrical isolation layer contacting the sub-collector. The heterojunction bipolar transistor may also include a backside heatsink thermally coupled to the sub-collector and the collector. The backside heatsink may be aligned with a central axis of the emitter and the base.