公开(公告)号：US12142510B2

公开(公告)日：2024-11-12

申请号：US17132429

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Michael J. Baker ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L21/683 ,  H01L21/67 ,  H01L23/00

Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.

公开(公告)号：US12062631B2

公开(公告)日：2024-08-13

申请号：US17025181

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A Elsherbini ,  Krishna Bharath ,  Kevin P. O'Brien ,  Kimin Jun ,  Han Wui Then ,  Mohammad Enamul Kabir ,  Gerald S. Pasdast ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/05147 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09055 ,  H01L2224/09505 ,  H01L2224/29186 ,  H01L2224/32145

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US12027466B2

公开(公告)日：2024-07-02

申请号：US17026703

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC: H01L23/538 ,  H01L21/768 ,  H05K1/11

CPC classification number: H01L23/5386 ,  H01L21/76838 ,  H01L23/5385 ,  H05K1/11

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US20240178162A1

公开(公告)日：2024-05-30

申请号：US18060125

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2223/6616

Abstract: An integrated circuit (IC) package substrate including a glass core having a cavity filter structure, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include a core made of glass, and the core including a first core portion having a first surface and a trench and a ridge in the first surface, the trench and the ridge lined with a conductive material; and a second core portion having a second surface, the second surface lined with the conductive material, wherein the first surface of the first core portion is physically coupled to the second surface of the second core portion forming a cavity filter structure.

公开(公告)号：US20240162157A1

公开(公告)日：2024-05-16

申请号：US17988051

申请日：2022-11-16

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon Christian Marin ,  Aleksandar Aleksov ,  Srinivas V. Pietambaram ,  Haobo Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L25/0655

Abstract: A bumpless hybrid organic glass interposer. One or more high density pattern (HDP) routing layers are placed on a functional, thin, carrier, separate from the intended organic substrate patch or package. The HDP layer(s) is/are then attached to the substrate package. The interposers achieve electrical connections between the HDP layer and underlying routing layer of the substrate package by utilizing a self-align dry etch process through landing pads connected to the HDP routing.

公开(公告)号：US20240071777A1

公开(公告)日：2024-02-29

申请号：US18502244

申请日：2023-11-06

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.

公开(公告)号：US20240006292A1

公开(公告)日：2024-01-04

申请号：US17856185

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L21/4857

Abstract: Disclosed herein are via-trace-via structures with improved alignment, and related devices and methods. For example, in some embodiments, an integrated circuit (IC) package support may include a conductive structure having an aperture; a conductive via at least partially nested in the aperture in the conductive structure; and a conductive bridge spanning between and in contact with the conductive structure and the conductive via. In some embodiments, the conductive structure is a conductive pad. In some embodiments, the conductive structure is a conductive plane.

公开(公告)号：US11837534B2

公开(公告)日：2023-12-05

申请号：US15859309

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Kristof Darmawikarta ,  Haobo Chen ,  Changhua Liu ,  Sri Ranga Sai Boyapati ,  Bai Nie

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822

Abstract: Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11830831B2

公开(公告)日：2023-11-28

申请号：US16327810

申请日：2016-09-23

Applicant: INTEL CORPORATION

Inventor： Georgios Dogiamis ,  Sasha Oster ,  Johanna Swan ,  Shawna Liff ,  Adel Elsherbini ,  Telesphor Kamgaing ,  Aleksandar Aleksov

IPC: H01L23/66 ,  H01P3/12

CPC classification number: H01L23/66 ,  H01P3/121 ,  H01L2223/6627

Abstract: Integration of a side-radiating waveguide launcher system into a semiconductor package beneficially permits the coupling of a waveguide directly to the semiconductor package. Included are a first conductive member and a second conductive member separated by a dielectric material. Also included is a conductive structure, such as a plurality of vias, that conductively couples the first conductive member and the second conductive member. Together, the first conductive member, the second conductive member, and the conductive structure form an electrically conductive side-radiating waveguide launcher enclosing shaped space within the dielectric material. The shaped space includes a narrow first end and a wide second end. An RF excitation element is disposed proximate the first end and a waveguide may be operably coupled proximate the second end of the shaped space.

公开(公告)号：US11784181B2

公开(公告)日：2023-10-10

申请号：US17580787

申请日：2022-01-21

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Feras Eid ,  Veronica Aleman Strong ,  Johanna M. Swan

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/24 ,  H01L29/861 ,  H01L29/47 ,  H01L29/872 ,  H01L29/45

CPC classification number: H01L27/0255 ,  H01L23/5286 ,  H01L27/0248 ,  H01L29/24 ,  H01L29/45 ,  H01L29/47 ,  H01L29/8613 ,  H01L29/872

Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.