公开(公告)号：US06573586B2

公开(公告)日：2003-06-03

申请号：US10081537

申请日：2002-02-25

申请人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

发明人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

IPC分类号： H01L2900

CPC分类号： H01L27/226 ,  B82Y10/00 ,  G11C11/16

摘要： Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the amplified current to an associated read data line.

公开(公告)号：US06512714B2

公开(公告)日：2003-01-28

申请号：US09942558

申请日：2001-08-31

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C702

CPC分类号： G11C11/4099 ,  G11C7/14

摘要： There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The memory cell is composed of a read NMOS transistor, a write transistor, and a coupled-capacitance. The dummy cell is made such that two memory cells are connected in series. The dummy cell is arranged at the most far end of each of the data lines against the sense amplifier. A reference voltage is generated by making a difference in an amount of current flowing in each of the read NMOS transistors of the memory cell and the dummy cell. As a result, DRAM showing a higher speed, a higher integration and a lower electrical power as compared with those of the prior art device can be realized.

摘要翻译： 提供了用于读出具有放大能力的存储单元的操作的参考电压产生方法和虚拟单元。 存储单元由读取NMOS晶体管，写入晶体管和耦合电容构成。 虚拟单元被制成使得两个存储单元串联连接。 每个数据线的最远端布置在相对于读出放大器的虚拟单元。 通过使存储单元的读取NMOS晶体管和虚设单元中的每一个中流动的电流量的差异来产生参考电压。 结果，可以实现与现有技术的装置相比显示更高速度，更高集成度和更低电力的DRAM。

公开(公告)号：US06281725B1

公开(公告)日：2001-08-28

申请号：US09337421

申请日：1999-06-22

申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Katsutaka Kimura

发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Katsutaka Kimura

IPC分类号： H03L700

CPC分类号： H03K5/135 ,  H03K5/133 ,  H03L7/0814 ,  H03L7/0818 ,  H04L7/0008

摘要： A clock recovery circuit is provided for use in a memory with a clock synchronized interface or the like, wherein an external clock is temporarily intercepted to shorten the lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, into which an external clock is inputted, for generating a plurality of reference clocks, a control circuit for comparing the phases of the external clock and of the plurality of reference clocks and detecting the number of delay stages of the delay circuits required for locking in, and latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected and the number of delay stages required for locking in are held in the latching circuit, the generation of the internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.

摘要翻译： 提供了一种用于具有时钟同步接口等的存储器中的时钟恢复电路，其中暂时截取外部时钟以缩短当从外部时钟产生内部时钟时的锁定时间。时钟恢复 电路包括：输入外部时钟的延迟电路阵列，用于产生多个参考时钟;控制电路，用于比较外部时钟和多个参考时钟的相位，并且检测所述多个参考时钟的延迟级数 锁定所需的延迟电路和用于保持锁定所需的延迟级数的锁存电路。一旦检测到同步，锁定所需的延迟级数被保持在锁存电路中，则产生内部时钟可以 即使暂时停止外部时钟的供给，也可以在短时间内恢复。

公开(公告)号：US06222792B1

公开(公告)日：2001-04-24

申请号：US09666598

申请日：2000-09-20

申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

摘要： A phase control circuit comprises a plurality of fixed delay circuits (200-0 through 200-5) which assign different predetermined delay times to a first clock signal (BDA1) respectively, a detection circuit (201) which receives clock signals outputted from the plurality of fixed delay circuits and a second clock signal (PCLK) different in phase from the first clock signal therein and generates detected signals (202) represented in a plurality of bits each corresponding to the difference in phase between the first clock signal and the second clock signal, and a variable delay circuit (200-6) which gives a delay in the phase difference corresponding to each of the detected signals to a third clock signal (BDA2).

公开(公告)号：US08799560B2

公开(公告)日：2014-08-05

申请号：US13389260

申请日：2010-06-18

申请人： Satoru Hanzawa

发明人： Satoru Hanzawa

IPC分类号： G06F12/00

CPC分类号： G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097

摘要： A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period. When the second storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a second period. By such a structure, the first period is shorter than the second period.

摘要翻译： 实现了高速大容量相变存储器。 根据本发明的半导体器件包括：多个存储器平面MP; 与多个存储器平面配对的多个存储信息寄存器组SDRBK; 和芯片控制电路CPCTL。 多个存储器平面包括多个存储单元。 此外，多个存储信息寄存器组临时保留要存储在多个存储器平面中的信息。 此外，芯片控制电路包括临时存储指示存储信息的卷的值的寄存器，并且第一存储信息量小于第二存储信息量。 当第一存储信息量被写入时，多个存储器平面和多个存储信息寄存器组在第一时段期间被激活。 当第二存储信息量被写入时，多个存储器平面和多个存储信息寄存器组在第二时段期间被激活。 通过这种结构，第一周期比第二周期短。

公开(公告)号：US08730717B2

公开(公告)日：2014-05-20

申请号：US13104005

申请日：2011-05-09

申请人： Satoru Hanzawa ,  Yoshitaka Sasago

发明人： Satoru Hanzawa ,  Yoshitaka Sasago

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/78 ,  H01L27/2454 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144

摘要： A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA).

摘要翻译： 半导体器件具有布置在多个字线和与字线相交的多个位线之间的交叉处的多个存储单元组。 存储单元组各自具有串联连接的第一和第二存储器单元。 第一和第二存储单元中的每一个具有并联连接的选择晶体管和电阻存储器件。 第一存储单元中的选择晶体管的栅电极与第一栅极线连接，第二存储单元中的选择晶体管的栅电极连接到第二栅极线。 用于驱动字线的第一电路块（字驱动器组WDBK）被布置在用于驱动第一和第二栅极线（相变型链单元控制电路PCCCTL）的第二电路块和多个存储单元组 阵列MA）。

公开(公告)号：US08699262B2

公开(公告)日：2014-04-15

申请号：US13270299

申请日：2011-10-11

申请人： Takao Watanabe ,  Satoru Hanzawa ,  Yoshitaka Sasago

发明人： Takao Watanabe ,  Satoru Hanzawa ,  Yoshitaka Sasago

IPC分类号： G11C11/24

CPC分类号： H01L45/06 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2481

摘要： Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.

摘要翻译： 驱动电路的寄生电阻和寄生电容对存储单元的不利影响引起对未选择单元的热扰动，施加电压的不均匀性，读取中存储元件的劣化的问题。 电容器（C）设置在存储单元（MC）的上方或下方，存储单元（MC）包括与存储元件连接的当前写入存储器信息和选择元件的存储元件。 存储在该电容器中的电荷写入存储器元件。

公开(公告)号：US08482997B2

公开(公告)日：2013-07-09

申请号：US13366329

申请日：2012-02-05

申请人： Satoru Hanzawa ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Saen

发明人： Satoru Hanzawa ,  Hitoshi Kume ,  Motoyasu Terao ,  Tomonori Sekiguchi ,  Makoto Saen

IPC分类号： G11C7/00 ,  G11C11/00 ,  H01L21/00

CPC分类号： G01R31/31715 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/72 ,  Y10T29/49169

摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。

公开(公告)号：US08427865B2

公开(公告)日：2013-04-23

申请号：US13440225

申请日：2012-04-05

申请人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： G11C11/00 ,  H01L29/80

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US08248843B2

公开(公告)日：2012-08-21

申请号：US12986178

申请日：2011-01-07

申请人： Satoru Hanzawa ,  Yoshikazu Iida

发明人： Satoru Hanzawa ,  Yoshikazu Iida

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C2213/79

摘要： In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.

摘要翻译： 在包括具有可变电阻的存储器件RQ和选择晶体管MQ的存储单元MC的存储器阵列MCA中，目的是在短时间内接收固定量的存储数据，并且实现对 存储单元，具有抑制的峰值电流。 为了实现该目的，通过使用多个读出放大器和临时存储存储数据来缩短重写操作中的数据总线占用时间，并且使用具有不同相位的控制信号来提供和激活多个编程电路。 通过上述，可以实现具有低电流消耗的相变存储器系统，而不会降低数据总线的利用率。