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    Memory access circuits and layout of the same for cross-point memory arrays
    62.
    发明申请
    Memory access circuits and layout of the same for cross-point memory arrays 审中-公开
    存储器访问电路和布局相同的交叉点存储器阵列

    公开(公告)号：US20100157647A1

    公开(公告)日：2010-06-24

    申请号：US12653898

    申请日：2009-12-18

    Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Chang Hua Siau

    Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Chang Hua Siau

    IPC: G11C5/02 ,  H01L27/00 ,  G11C8/10

    CPC classification number: G11C8/10 ,  G11C5/02 ,  G11C5/025 ,  H01L27/0688

    Abstract: An integrated circuit includes a substrate including active circuitry fabricated on the substrate and a cross-point memory array formed above the substrate. The cross-point memory array can include conductive array lines arranged in different directions, and re-writable memory cells. Further, the integrated circuit can also include a memory access circuit configured to perform data operations on the cross-point memory array. The integrated circuit can include a cross-point memory array interface layer positioned between the substrate and the cross-point array and including conductive paths configured to electrically couple portions of the memory access circuit with a subset of the conductive array lines. At least one layer of cross-point memory arrays can be formed over the substrate. The memory cells can be two-terminal memory cells that store data as a plurality of conductivity profiles (e.g., resistive states) that can be non-destructively determined by applying a read voltage across the terminals.

    Abstract translation: 集成电路包括：衬底，其包括在衬底上制造的有源电路和形成在衬底上方的交叉点存储器阵列。 交叉点存储器阵列可以包括布置在不同方向的导电阵列线以及可重写存储器单元。 此外，集成电路还可以包括被配置为在交叉点存储器阵列上执行数据操作的存储器访问电路。 集成电路可以包括位于衬底和交叉点阵列之间的交叉点存储器阵列接口层，并且包括被配置为将存储器访问电路的一部分与导电阵列线的子集电耦合的导电路径。 可以在衬底上形成至少一层交叉点存储器阵列。 存储器单元可以是将数据存储为可以通过跨终端施加读取电压而非破坏性地确定的多个电导率分布（例如电阻状态）的两端存储单元。

    Memory using variable tunnel barrier widths
    63.
    发明申请
    Memory using variable tunnel barrier widths 失效
    使用可变隧道势垒宽度的内存

    公开(公告)号：US20090231906A1

    公开(公告)日：2009-09-17

    申请号：US12454698

    申请日：2009-05-21

    Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Edmond Ward

    Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Edmond Ward

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/02 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/71 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2481 ,  H01L29/8616 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    Abstract: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.

    Abstract translation: 公开了一种使用具有可变有效宽度的隧道势垒的存储器。 存储元件包括隧道势垒和导电材料。 导电材料通常具有响应于存储元件两端的电压而移动或者远离隧道势垒的移动离子。 形成或破坏低导电性区域。 它可以通过隧道势垒周围的耗尽或过量离子，或通过与互补离子组合的移动离子来形成。 可能通过反转成形过程或减少隧道势垒并将离子注入导电材料来破坏。 低导电率区域增加了隧道势垒的有效宽度，使得电子隧道更大的距离，这降低了存储元件的导电性。 通过改变电导率，可以在存储器单元中产生多个状态。

    Method for sensing a signal in a two-terminal memory array having leakage current
    65.
    发明授权
    Method for sensing a signal in a two-terminal memory array having leakage current 有权
    用于感测具有漏电流的双端存储器阵列中的信号的方法

    公开(公告)号：US07505347B2

    公开(公告)日：2009-03-17

    申请号：US12072813

    申请日：2008-02-28

    Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Chang Hua Siau

    Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Chang Hua Siau

    IPC: G11C7/02

    CPC classification number: G11C11/16 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2211/5634 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/77

    Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

    Abstract translation: 双端存储器阵列包括多个第一和第二导电迹线。 地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。 在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读取操作中由感测单元感测。 总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。 电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

    Threshold device for a memory array
    67.
    发明申请
    Threshold device for a memory array 失效
    内存阵列的阈值设备

    公开(公告)号：US20090027976A1

    公开(公告)日：2009-01-29

    申请号：US11881473

    申请日：2007-07-26

    Applicant: Julie Casperson Brewer ,  Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    Inventor： Julie Casperson Brewer ,  Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    IPC: G11C7/00

    CPC classification number: G11C7/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

    Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

    Abstract translation: 公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。 具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。 阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。 阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。 阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

    Enhanced functionality in a two-terminal memory array
    69.
    发明授权
    Enhanced functionality in a two-terminal memory array 有权
    两端存储器阵列中增强的功能

    公开(公告)号：US07330370B2

    公开(公告)日：2008-02-12

    申请号：US11021600

    申请日：2004-12-23

    Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Steven W. Longcor ,  Edmond Ward ,  Robert Norman

    Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Steven W. Longcor ,  Edmond Ward ,  Robert Norman

    IPC: G11C11/00

    CPC classification number: G11C11/16

    Abstract: A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory element electrodes are employed to store nonvolatile information. The array has at least one enhanced functionality portion that performs operations selected from the group consisting of reference, error correction, device specific storage, defect mapping tables, and redundancy.

    Abstract translation: 介绍了增强功能的内存阵列。 阵列中的每个单元包括一对存储元件电极。 一对存储元件电极上的读取电流表示存储的信息，并且跨该对存储元件电极的不同写入电压电平被用于存储非易失性信息。 该阵列具有至少一个增强功能部分，其执行从由参考，纠错，设备特定存储，缺陷映射表和冗余组成的组中选择的操作。

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