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    Avoiding unintentional program or erase of a select gate transistor
    51.
    发明授权
    Avoiding unintentional program or erase of a select gate transistor 有权
    避免无意的编程或擦除选择栅晶体管

    公开(公告)号：US09343159B2

    公开(公告)日：2016-05-17

    申请号：US14465244

    申请日：2014-08-21

    Applicant: SanDisk Technologies Inc.

    Inventor： Yingda Dong ,  Liang Pang

    IPC: G11C16/16 ,  G11C16/14 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34

    CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3445

    Abstract: Techniques are provided for preventing inadvertent program or erase of select gate transistors and dummy memory cells during an erase operation involving data-storing memory cells in a three-dimensional memory device. The erase operation charges up a channel of a NAND string using gate-induced drain leakage from the select gate transistors. An erase voltage waveform and a select gate waveform are ramped up to intermediate levels which allow some charging of the channel to occur. The intermediate level of the select gate waveform is low enough to avoid inadvertent programming of the select gate transistors. Subsequently, the erase voltage waveform and the select gate waveform are ramped up to peak levels which allow additional charging of the channel to occur. The peak levels are set to avoid inadvertent erasing of the select gate transistors.

    Abstract translation: 提供技术用于在涉及在三维存储器件中存储存储单元的数据存储单元的擦除操作期间防止选择栅极晶体管和虚设存储单元的意外编程或擦除。 擦除操作使用来自选择栅极晶体管的栅极引起的漏极泄漏来对NAND串的通道充电。 擦除电压波形和选择栅极波形斜坡上升到允许通道发生一些充电的中间电平。 选择栅极波形的中间电平足够低以避免选择栅极晶体管的无意编程。 随后，擦除电压波形和选择栅极波形斜坡上升到峰值电平，这允许发生信道的附加充电。 设置峰值电平以避免选择栅极晶体管的无意擦除。

    METHOD OF ERASING INFORMATION AND DEVICE FOR PERFORMING SAME
    52.
    发明申请
    METHOD OF ERASING INFORMATION AND DEVICE FOR PERFORMING SAME 有权
    消除信息的方法和执行其的设备

    公开(公告)号：US20160133331A1

    公开(公告)日：2016-05-12

    申请号：US15001054

    申请日：2016-01-19

    Applicant: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.

    Inventor： Stefan HOEFFGEN ,  Michael JOESTER ,  Jochen KUHNHENN ,  Tobias KUENDGEN ,  Stefan METZGER

    IPC: G11C16/18 ,  G11C16/04

    CPC classification number: G11C16/18 ,  G11C11/5635 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/16

    Abstract: Methods and devices for erasing information stored on an electronic semiconductor component in a plurality of non-volatile memory elements are described. Irradiating the semiconductor component with erasing radiation until a target dose has been absorbed by the semiconductor component, the erasing radiation penetrating the semiconductor component, results in an ionization effect which influences the concentration of the charge carriers stored on the memory elements such that a statistical distribution of the threshold voltages of the memory elements forms a contiguous region.

    Abstract translation: 描述用于擦除存储在多个非易失性存储器元件中的电子半导体部件上的信息的方法和装置。 用半导体元件对半导体元件进行辐射辐射直到目标剂量被半导体元件吸收，穿透半导体元件的擦除辐射导致电离效应，其影响存储在存储器元件上的电荷载流子的浓度，从而统计分布 的存储元件的阈值电压形成连续区域。

    Group word line erase and erase-verify methods for 3D non-volatile memory
    53.
    发明授权
    Group word line erase and erase-verify methods for 3D non-volatile memory 有权
    用于3D非易失性存储器的组字线擦除和擦除验证方法

    公开(公告)号：US09330778B2

    公开(公告)日：2016-05-03

    申请号：US14524153

    申请日：2014-10-27

    Applicant: SanDisk Technologies Inc.

    Inventor： Xiying Costa ,  Alex Mak ,  Johann Alsmeier ,  Man L Mui

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/14 ,  G11C11/56 ,  G11C16/04 ,  H01L27/115

    CPC classification number: G11C16/3445 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11582

    Abstract: An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

    Abstract translation: 3D堆叠存储器件的擦除操作根据预期的擦除速度将存储元件分配给组。 然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。 在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。 可以将所有组一起设置为擦除或禁止状态。 在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

    METHODS OF OPERATING A NONVOLATILE MEMORY DEVICE
    55.
    发明申请
    METHODS OF OPERATING A NONVOLATILE MEMORY DEVICE 有权
    操作非易失性存储器件的方法

    公开(公告)号：US20160111165A1

    公开(公告)日：2016-04-21

    申请号：US14859637

    申请日：2015-09-21

    Applicant: Sunil SHIM ,  Joon-sung LIM ,  Jin-Kyu KANG ,  Euido KIM ,  Jang-Gn YUN

    Inventor： Sunil SHIM ,  Joon-sung LIM ,  Jin-Kyu KANG ,  Euido KIM ,  Jang-Gn YUN

    IPC: G11C16/16 ,  G11C16/34

    CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/3445

    Abstract: An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed.

    Abstract translation: 提供一种非易失性存储装置的操作方法，其顺序地执行多个擦除循环以擦除多个存储块中的至少一个。 所述操作方法包括执行所述多个擦除环中的至少一个; 在执行所述至少一个擦除循环之后对所述至少一个存储器块执行后编程操作; 以及执行所述多个擦除环路的剩余擦除环路。 当执行每个剩余擦除循环时，不执行后编程操作。

    NON-VOLATILE SEMICONDUCTOR MEMORY WITH HIGH RELIABILITY AND DATA ERASING METHOD THEREOF
    56.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY WITH HIGH RELIABILITY AND DATA ERASING METHOD THEREOF 有权
    具有高可靠性和数据擦除方法的非易失性半导体存储器

    公开(公告)号：US20160099064A1

    公开(公告)日：2016-04-07

    申请号：US14729066

    申请日：2015-06-03

    Applicant: Winbond Electronics Corp.

    Inventor： Riichiro Shirota

    IPC: G11C16/14 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3445

    Abstract: A non-volatile semiconductor memory apparatus and a data erasing method thereof are provided to suppress deterioration in reliability due to data rewriting. An erasing method of a flash memory is provided, which includes the following steps. A control gate is maintained at 0V, a high-voltage erase pulse is applied to a P well, such that electrons is emitted from a floating gate to the P well. Then, the control gate is again maintained, and a weak erase pulse with a voltage lower than the erase pulse is applied to the P well.

    Abstract translation: 提供一种非易失性半导体存储装置及其数据擦除方法，以抑制由于数据重写导致的可靠性劣化。 提供了一种闪存的擦除方法，其包括以下步骤。 控制栅极保持在0V，高压擦除脉冲施加到P阱，使得电子从浮动栅极发射到P阱。 然后，再次保持控制栅极，并且将具有低于擦除脉冲的电压的弱擦除脉冲施加到P阱。

    FAST SECURE ERASE IN A FLASH SYSTEM
    57.
    发明申请
    FAST SECURE ERASE IN A FLASH SYSTEM 有权
    快速安全擦除闪存系统

    公开(公告)号：US20160099061A1

    公开(公告)日：2016-04-07

    申请号：US14506488

    申请日：2014-10-03

    Applicant: HGST Netherlands B.V.

    Inventor： Pablo A. ZIPEROVICH

    IPC: G11C16/14 ,  G11C16/34

    CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/12 ,  G11C16/14 ,  G11C16/3445

    Abstract: A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.

    Abstract translation: 闪速存储器控制器被配置为提供第一擦除模式，用于使用多个擦除脉冲擦除闪存器件中的一组或多组闪速存储器单元，以及第二擦除模式，用于擦除一组或多组闪存单元， 单个擦除脉冲。 控制器可以接收快速擦除信号以擦除一组或多组闪速存储器单元，并且响应于该信号，从对应于第一擦除模式的第一参数切换闪速存储器件的操作参数到对应于第一擦除模式的第二参数 第二擦除模式，并且根据第二参数指示闪速存储器件对一组或多组闪存单元执行擦除操作。 然后，控制器可以使用单个擦除脉冲来验证擦除操作是否完成。

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