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139 条记录 (耗时 0.03 秒)

    Overlay mark
    51.
    发明授权
    Overlay mark 有权

    公开(公告)号：US10424543B2

    公开(公告)日：2019-09-24

    申请号：US16207056

    申请日：2018-11-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chen-Yu Chen ,  Ming-Feng Shieh ,  Ching-Yu Chang

    IPC分类号： H01L23/544 ,  G03F7/20 ,  H01L21/302 ,  H01L29/06 ,  H01L29/78

    摘要： A method of forming an overlay mark includes disposing a first feature of a plurality of first alignment segments extending along a first direction in a first layer, disposing a second feature of a plurality of second alignment segments extending along a second direction in a second layer over the first layer, and forming a third feature of a plurality of third alignment segments extending along the first direction and a plurality of fourth alignment segments extending along the second direction in a third layer over the second layer. In a plan view, each first alignment segment of the first alignment segments is adjacent to a corresponding third alignment segment of the third alignment segments along the first direction, and each second alignment segment of the second alignment segments is adjacent to a corresponding fourth alignment segment of the fourth alignment segments along the second direction.

    Method and apparatus of patterning a semiconductor device
    53.
    发明授权
    Method and apparatus of patterning a semiconductor device 有权

    公开(公告)号：US10048590B2

    公开(公告)日：2018-08-14

    申请号：US14727317

    申请日：2015-06-01

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chien-Wei Wang ,  Ming-Feng Shieh ,  Ching-Yu Chang

    IPC分类号： G03F7/42 ,  G03F7/40 ,  G03F7/004 ,  G03F7/039 ,  G03F7/038 ,  H01L21/311 ,  H01L21/306

    摘要： Provided is a photoresist that includes a polymer having a backbone that is breakable and a photo acid generator that is free of bonding from the polymer. Further, provided is a method of fabricating a semiconductor device. The method includes providing a device substrate. A material layer is formed over the substrate. A photoresist material is formed over the material layer. The photoresist material has a polymer that includes a backbone. The photoresist material is patterned to form a patterned photoresist layer. A fabrication process is then performed to the material layer, wherein the patterned photoresist layer serves as a mask in the fabrication process. Thereafter, the patterned photoresist layer is treated in a manner that breaks the backbone of the polymer. The patterned photoresist layer is then removed.

    Method for integrated circuit patterning
    56.
    发明授权
    Method for integrated circuit patterning 有权
    集成电路图案化方法

    公开(公告)号：US09466486B2

    公开(公告)日：2016-10-11

    申请号：US14014771

    申请日：2013-08-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ming-Feng Shieh ,  Ru-Gun Liu ,  Hung-Chang Hsieh ,  Tien-I Bao ,  Chung-Ju Lee ,  Shau-Lin Shue

    IPC分类号： H01L21/308 ,  H01L21/311 ,  G03F7/26 ,  H01L21/033 ,  H01L21/768 ,  H01L29/66

    CPC分类号： H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/66795

    摘要： A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate.

    摘要翻译： 形成目标图案的方法包括：在切割掩模的基板中形成第一沟槽; 用第一主掩模在衬底上形成第一多条线，其中第一主掩模包括与第一沟槽重叠的至少一条线，由此由第一沟槽切割成至少两条线; 在所述基板上形成间隔层，并且在所述第一多条线路中的所述第一多条线路和所述侧壁上形成间隔层; 通过第二主掩模在间隔层上形成图案化材料层，由此图案化材料层和间隔层共同限定第二多个沟槽; 去除所述间隔层的至少一部分以暴露所述第一多条线; 并且去除第一多个线，从而在衬底上形成图案化间隔层。

    Mechanisms for Forming Patterns Using Lithography Processes
    58.
    发明申请
    Mechanisms for Forming Patterns Using Lithography Processes 审中-公开
    使用光刻工艺形成图案的机制

    公开(公告)号：US20160155639A1

    公开(公告)日：2016-06-02

    申请号：US15005861

    申请日：2016-01-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

    IPC分类号： H01L21/033

    CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/30625 ,  H01L21/3065

    摘要： The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

    摘要翻译： 本公开提供了一种用于在半导体器件中形成图案的方法。 根据一些实施例，所述方法包括在所述图案化目标层上方提供衬底，所述衬底上的图案化目标层和硬掩模层; 在硬掩模层中形成第一图案; 从所述硬掩模层中的所述第一图案移除修剪部分以形成修剪的第一图案; 在所述硬掩模层上形成第一抗蚀剂层; 在第一抗蚀剂层中形成主图案; 并且使用主图案和修剪的第一图案作为蚀刻掩模元件来蚀刻图案化目标层，以在图案化目标层中形成最终图案。 在一些实施例中，最终图案包括主图案，减去主图案和经修剪的第一图案之间的第一重叠部分。

    Mechanisms for forming patterns using multiple lithography processes
    59.
    发明授权
    Mechanisms for forming patterns using multiple lithography processes 有权
    使用多个光刻工艺形成图案的机制

    公开(公告)号：US09245763B2

    公开(公告)日：2016-01-26

    申请号：US14210032

    申请日：2014-03-13

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

    IPC分类号： H01L21/44 ,  H01L21/308 ,  H01L21/02 ,  H01L21/306

    CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/30625 ,  H01L21/3065

    摘要： The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

    摘要翻译： 本公开提供了一种用于在半导体器件中形成图案的方法。 根据一些实施例，所述方法包括在所述图案化目标层上方提供衬底，所述衬底上的图案化目标层和硬掩模层; 在硬掩模层中形成第一图案; 从所述硬掩模层中的所述第一图案移除修剪部分以形成修剪的第一图案; 在所述硬掩模层上形成第一抗蚀剂层; 在第一抗蚀剂层中形成主图案; 并且使用主图案和修剪的第一图案作为蚀刻掩模元件来蚀刻图案化目标层，以在图案化目标层中形成最终图案。 在一些实施例中，最终图案包括主图案，减去主图案和经修剪的第一图案之间的第一重叠部分。

    Self-Aligned Semiconductor Fabrication With Fosse Features
    60.
    发明申请
    Self-Aligned Semiconductor Fabrication With Fosse Features 有权
    具有Fosse特性的自对准半导体制造

    公开(公告)号：US20150318209A1

    公开(公告)日：2015-11-05

    申请号：US14266878

    申请日：2014-05-01

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Chih-Ming Lai ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tsai-Sheng Gau

    IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L21/311

    CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283

    摘要： The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.

    摘要翻译： 本公开描述了将期望的布局转移到半导体衬底上的目标层中的方法。 所述方法的一个实施例包括在目标层上形成第一期望布局特征作为第一行; 在第一条线周围形成间隔物; 沉积间隔物周围的材料层; 去除所述间隔物以形成围绕所述第一线的顶点图案沟槽; 以及将所述花纹图案沟槽转移到所述目标层中，以在所述目标层中形成顶点特征沟槽，其中所述特征沟槽围绕所述目标层的位于保护层下方的第一部分。 在一些实施例中，该方法还包括将期望布局的第二所需布局特征图案化成目标层，其中，所述优点特征沟槽和所述保护层用于使所述第二期望布局特征与所述目标层的所述第一部分自对准。