公开(公告)号：US11444162B2

公开(公告)日：2022-09-13

申请号：US17159423

申请日：2021-01-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Ming Lee ,  Wei-Yang Lee

IPC分类号： H01L29/40 ,  H01L21/283 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L21/3213

摘要： A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.

公开(公告)号：US11362199B2

公开(公告)日：2022-06-14

申请号：US16382860

申请日：2019-04-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Hsieh Wong ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

摘要： In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

公开(公告)号：US11296077B2

公开(公告)日：2022-04-05

申请号：US16429253

申请日：2019-06-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Ting Chen ,  Bo-Yu Lai ,  Chien-Wei Lee ,  Hsueh-Chang Sung ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/3065

摘要： A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

公开(公告)号：US11217486B2

公开(公告)日：2022-01-04

申请号：US16290760

申请日：2019-03-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Yu Yang ,  Feng-Cheng Yang ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Yen-Ting Chen

IPC分类号： H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  H01L21/762

摘要： A semiconductor device including a fin field effect transistor (FinFET) with a cut metal gate (CMG) and a method of manufacturing the semiconductor device are described herein. The method includes forming a CMG protective helmet structure at a top portion of a CMG dummy gate plug formed within a semiconductor substrate. The CMG protective helmet structure prevents consumption and damage of a dummy filler material in a CMG region and prevents undesirable polymer/residue byproducts from forming on top surfaces of epitaxial regions of the FinFET during etching processes.

公开(公告)号：US11205597B2

公开(公告)日：2021-12-21

申请号：US16458437

申请日：2019-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Chun Tan ,  I-Hsieh Wong ,  Te-En Cheng ,  Yung-Hui Lin ,  Wei-Ken Lin ,  Wei-Yang Lee ,  Chih-Hung Nien

IPC分类号： H01L21/311 ,  H01L29/16 ,  H01L27/092 ,  H01L29/06 ,  H01L21/306 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/265 ,  H01L21/308 ,  H01L21/3115 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/08 ,  H01L21/027 ,  H01L21/762 ,  H01L21/266 ,  H01L29/36

摘要： A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.

公开(公告)号：US10153344B2

公开(公告)日：2018-12-11

申请号：US15707886

申请日：2017-09-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165

摘要： Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US20160204229A1

公开(公告)日：2016-07-14

申请号：US15076061

申请日：2016-03-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC分类号： H01L29/66 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

CPC分类号： H01L29/0847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/32 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

摘要： Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US20150270342A1

公开(公告)日：2015-09-24

申请号：US14222401

申请日：2014-03-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC分类号： H01L29/08 ,  H01L21/02 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/0847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/32 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

摘要： Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

摘要翻译： 提供了在finFET器件的源极和漏极区域中形成位错的机构的实施例。 这些机构涉及凹陷翅片并去除隔离结构相邻鳍片中的电介质材料，以增加位错形成的外延区域。 这些机制还涉及在凹入的源极和漏极区域中的外延生长之前或之后进行预非晶注入（PAI）工艺。 在PAI工艺之后的退火工艺可以实现源极和漏极区域中位错的一致生长。 源极和漏极区域（或应力区域）中的位错可以一致地形成，以在源极和漏极区域中产生靶向应变，以改善NMOS器件的载流子迁移率和器件性能。

公开(公告)号：US20240363715A1

公开(公告)日：2024-10-31

申请号：US18770177

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ting-Yeh Chen ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/823418 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/78696

摘要： In an exemplary aspect, the present disclosure is directed to a device. The device includes a fin-shaped structure extending lengthwise along a first direction. The fin-shaped structure includes a stack of semiconductor layers arranged one over another along a second direction perpendicular to the first direction. The device also includes a first source/drain feature of a first dopant type on the fin-shaped structure and spaced away from the stack of semiconductor layers. The device further includes a second source/drain feature of a second dopant type on the fin-shaped structure over the first source/drain feature along the second direction and connected to the stack of semiconductor layers. The second dopant type is different from the first dopant type. Furthermore, the device additionally includes an isolation feature interposing between the first source/drain feature and the second source/drain features.

公开(公告)号：US20240339541A1

公开(公告)日：2024-10-10

申请号：US18745323

申请日：2024-06-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC分类号： H01L29/78 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/7856 ,  H01L21/3065 ,  H01L21/32134 ,  H01L21/76224 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.