公开(公告)号：US20140239402A1

公开(公告)日：2014-08-28

申请号：US13779015

申请日：2013-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7842 ,  H01L21/02532 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/157 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Abstract translation: 一种器件包括衬底和衬底的一部分上的绝缘区域。 第一半导体区域在绝缘区域之间并且具有第一导带。 第二半导体区域在第一半导体区域的上方并且邻接，其中第二半导体区域包括高于绝缘区域的顶表面的上部，以形成半导体鳍片。 半导体鳍具有拉伸应变，并且具有比第一导带低的第二导带。 第三半导体区域在半导体鳍片的上表面和侧壁的上方邻接，其中第三半导体区域具有比第二导带高的第三导带。

公开(公告)号：US20140220751A1

公开(公告)日：2014-08-07

申请号：US13794703

申请日：2013-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02647

Abstract: A method includes recessing a portion of a semiconductor substrate between opposite isolation regions to form a recess. After the step of recessing, the portion of the semiconductor substrate includes a top surface. The top surface includes a flat surface, and a slant surface having a (111) surface plane. The slant surface has a bottom edge connected to the flat surface, and a top edge connected to one of the isolation regions. The method further includes performing an epitaxy to grow a semiconductor material in the recess, wherein the semiconductor material is grown from the flat surface and the slant surface, and performing an annealing on the semiconductor material.

Abstract translation: 一种方法包括将半导体衬底的一部分凹入相对的隔离区域之间以形成凹部。 在凹陷步骤之后，半导体衬底的一部分包括顶表面。 顶表面包括平坦表面和具有（111）表面的倾斜表面。 倾斜表面具有连接到平坦表面的底部边缘，以及连接到隔离区域之一的顶部边缘。 该方法还包括执行外延以在凹槽中生长半导体材料，其中半导体材料从平坦表面和倾斜表面生长，并对半导体材料进行退火。

公开(公告)号：US20140217499A1

公开(公告)日：2014-08-07

申请号：US13757615

申请日：2013-02-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/20

CPC classification number: H01L29/20 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/762 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate. The portion of the semiconductor substrate has a (111) surface and a bottom surface. The (111) surface is slanted and has a top edge and a bottom edge. The bottom surface is parallel to a top surface of the insulation regions, and is connected to the bottom edge. A semiconductor region overlaps the portion of the semiconductor substrate, wherein the semiconductor region includes a second semiconductor material different from the first semiconductor material. The top edge and the bottom edge of the (111) surface are at a first depth and a second depth, respectively, relative to a top surface of the semiconductor region. A ratio of the first depth to the second depth is smaller than about 0.6.

Abstract translation: 一种结构包括包括第一半导体材料的半导体衬底。 半导体衬底的一部分在半导体衬底的绝缘区域之间延伸。 半导体衬底的一部分具有（111）表面和底表面。 （111）表面是倾斜的并且具有顶部边缘和底部边缘。 底表面平行于绝缘区域的顶表面，并连接到底部边缘。 半导体区域与半导体衬底的部分重叠，其中半导体区域包括与第一半导体材料不同的第二半导体材料。 （111）表面的顶边缘和底边分别相对于半导体区域的顶表面分别处于第一深度和第二深度。 第一深度与第二深度之比小于约0.6。

公开(公告)号：US20140138742A1

公开(公告)日：2014-05-22

申请号：US14078141

申请日：2013-11-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Yao-Tsung Huang ,  Cheng-Ying Huang

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A device including a silicon substrate, a silicon germanium layer, a silicon layer, a gate stack, and silicon-containing stressors is provided. In an embodiment, the silicon germanium layer is disposed over a silicon substrate and relaxed while the silicon layer is disposed over the silicon germanium layer and un-relaxed. The silicon layer may be free from germanium. The gate stack is of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) and disposed over the silicon layer and the silicon germanium layer. A portion of the silicon layer forms a channel region of the NMOS FET. The silicon-containing stressors are formed in recesses in the silicon layer and have a lattice constant smaller than a lattice constant of the silicon germanium layer.

Abstract translation: 提供了包括硅衬底，硅锗层，硅层，栅叠层和含硅应力源的器件。 在一个实施例中，硅锗层设置在硅衬底上并且松弛，同时硅层设置在硅锗层上并且不放松。 硅层可以不含锗。 栅极堆叠是n型金属氧化物半导体（NMOS）场效应晶体管（FET）并且设置在硅层和硅锗层之上。 硅层的一部分形成NMOS FET的沟道区。 含硅应力源形成在硅层中的凹陷中，其晶格常数小于硅锗层的晶格常数。

公开(公告)号：US20140134815A1

公开(公告)日：2014-05-15

申请号：US14157638

申请日：2014-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L29/66

CPC classification number: H01L29/8124 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/66431 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/812

Abstract: A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.

Abstract translation: 多栅极晶体管包括在衬底上的半导体鳍。 半导体鳍片包括由第一半导体材料形成的中心鳍片; 以及半导体层，其具有在中心散热片的相对侧壁上的第一部分和第二部分。 半导体层包括与第一半导体材料不同的第二半导体材料。 多栅极晶体管还包括围绕半导体鳍片的侧壁的栅电极; 以及在半导体鳍片的相对端上的源极区域和漏极区域。 中央翅片和半导体层中的每一个从源极区域延伸到漏极区域。

公开(公告)号：US20140033981A1

公开(公告)日：2014-02-06

申请号：US14046360

申请日：2013-10-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC: H01L21/02 ,  C30B25/10

CPC classification number: H01L21/0262 ,  C30B25/105 ,  C30B25/186 ,  C30B29/40 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/76224

Abstract: A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).

Abstract translation: 一种器件包括提供硅衬底; 在高于约900℃的第一温度下退火硅衬底; 以及将所述硅衬底的温度从所述第一温度降低到第二温度。 在降低温度的步骤期间的降温速率大于约1℃/秒。 使用金属有机化学气相沉积（MOCVD）在硅衬底的表面上外延生长III-V族化合物半导体区域。

公开(公告)号：US20130132923A1

公开(公告)日：2013-05-23

申请号：US13742165

申请日：2013-01-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Clement Hsingjen Wann

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method for constant power density scaling in MOSFETs is provided. A method for manufacturing an integrated circuit includes computing fixed scaling factors for a first fabrication process based on a second fabrication process, computing settable scaling factors for the integrated circuit to be fabricated using the first fabrication process, determining parameters of the integrated circuit based on the settable scaling factors, and manufacturing the integrated circuit using the determined parameters. The first fabrication process creates devices having a smaller device dimension than the second fabrication process and the settable scaling factors are set based on the fixed scaling factors.

Abstract translation: 提供了一种用于MOSFET中恒定功率密度缩放的方法。 一种用于制造集成电路的方法包括：基于第二制造工艺计算用于第一制造工艺的固定缩放因子，使用第一制造工艺计算待制造的集成电路的可设定缩放因子，基于 可设置的缩放因子，并使用确定的参数制造集成电路。 第一制造工艺产生具有比第二制造工艺更小的装置尺寸的装置，并且可固定缩放因子基于固定缩放因子设定。

公开(公告)号：US12183802B2

公开(公告)日：2024-12-31

申请号：US17510105

申请日：2021-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yi-Jing Li ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.

公开(公告)号：US12119389B2

公开(公告)日：2024-10-15

申请号：US18360854

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hsiung Tsai ,  Kuo-Feng Yu ,  Yu-Ming Lin ,  Clement Hsingjen Wann

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/08 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02332 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66795 ,  H01L21/266 ,  H01L21/31053 ,  H01L21/76224 ,  H01L29/665

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.

公开(公告)号：US11972982B2

公开(公告)日：2024-04-30

申请号：US17865311

申请日：2022-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun Hsiung Tsai ,  Yu-Ming Lin ,  Kuo-Feng Yu ,  Ming-Hsi Yeh ,  Shahaji B. More ,  Chandrashekhar Prakash Savant ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC: H01L21/82 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/02057 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/324

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.