公开(公告)号：US20240172428A1

公开(公告)日：2024-05-23

申请号：US18518293

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： KYUNGHWAN KIM ,  Hyungeun Choi ,  Keunnam Kim ,  Seokhan Park ,  Seokho Shin ,  Joongchan Shin ,  Kiseok Lee ,  Sangho Lee ,  Moonyoung Jeong

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device is provided. The semiconductor device includes: a lower structure including a bit line; a cell semiconductor body vertically overlapping the bit line, on the lower structure; a peripheral semiconductor body including a portion disposed on a same level as at least a portion of the cell semiconductor body, on the lower structure; and a peripheral gate on the peripheral semiconductor body, wherein the peripheral semiconductor body includes a lower region having a first width and an upper region having a second width, greater than the first width on the lower region.

公开(公告)号：US20230354582A1

公开(公告)日：2023-11-02

申请号：US18062825

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Byeongjoo Ku ,  Keunnam Kim ,  Wonsok Lee ,  Moonyoung Jeong ,  Min Hee Cho

IPC: H01L29/94

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion to be adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the horizontal portion may be located at a height that is lower than or equal to the uppermost surface of the bit line.

公开(公告)号：US11688687B2

公开(公告)日：2023-06-27

申请号：US17198591

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H10B12/03 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34 ,  H10B12/48 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50 ,  H01L21/76807 ,  H10B12/053

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US20230178505A1

公开(公告)日：2023-06-08

申请号：US18050497

申请日：2022-10-28

Applicant: Samsung Electronics Co.. Ltd.

Inventor： KISEOK LEE ,  Hyungeun Choi ,  Gijae Kang ,  Keunnam Kim ,  Soobin Yim ,  Moonyoung Jeong ,  Seungjae Jung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H10B12/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/80 ,  H01L25/50 ,  H01L27/10805 ,  H01L27/10897 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Semiconductor memory devices may include a cell array structure that may include a memory cell array including three-dimensionally arranged memory cells and first bonding pads connected to the memory cell array and a peripheral circuit structure that may include peripheral circuits and second bonding pads bonded to the first bonding pads. The cell array structure may include a lower dielectric layer having a first surface and a second surface opposite to the first surface, a stack structure including horizontal electrodes stacked in a vertical direction on the first surface of the lower dielectric layer, a vertical structure including vertical conductive patterns that extend in the vertical direction and cross the horizontal electrodes, and an input/output pad on the second surface of the lower dielectric layer.

公开(公告)号：US11658117B2

公开(公告)日：2023-05-23

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L27/10888 ,  H01L29/0649 ,  H01L29/4236

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US11646225B2

公开(公告)日：2023-05-09

申请号：US17039431

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

IPC: H01L27/10 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US11521977B2

公开(公告)日：2022-12-06

申请号：US17471824

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US11502082B2

公开(公告)日：2022-11-15

申请号：US16902338

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

公开(公告)号：US20220165657A1

公开(公告)日：2022-05-26

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEJIN PARK ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20220139921A1

公开(公告)日：2022-05-05

申请号：US17372634

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd

Inventor： EUNA KIM ,  Keunnam Kim ,  Kiseok Lee ,  Wooyoung Choi ,  Sunghee Han

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.