公开(公告)号：US20150303148A1

公开(公告)日：2015-10-22

申请号：US14254764

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Robert Paul Mikulka

IPC: H01L23/552 ,  H01L23/00 ,  H05K9/00 ,  H01L23/04 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/32 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01R12/7076 ,  H01R12/714 ,  H05K1/181 ,  H05K9/0032 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.

Abstract translation: 一些新颖特征涉及包括封装衬底，管芯，封装层和第一组金属层的集成器件封装（例如管芯封装）。 封装衬底包括第一表面和第二表面。 管芯耦合到封装衬底的第一表面。 封装层封装模具。 第一组金属层耦合到封装层的第一外表面。 在一些实施方案中，第一组金属层被配置为作为集成器件封装的管芯到线连接器工作。 在一些实施方案中，集成器件封装包括耦合到封装衬底的第二表面的第二组金属层。 在一些实施方案中，集成器件封装包括耦合到封装层的第二外表面的第二组金属层。

公开(公告)号：US09135976B2

公开(公告)日：2015-09-15

申请号：US14104443

申请日：2013-12-12

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Kendrick Hoy Leong Yuen ,  Xiaochun Zhu ,  Seung Hyuk Kang ,  Matthew Michael Nowak ,  Jeffrey Alexander Levin ,  Robert P. Gilmore ,  Nicholas Ka Ming Yu

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  G11C11/54

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/54 ,  G11C11/5607

Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Abstract translation: 将概率编程电流注入到双稳定概率开关元件簇中，概率编程电流具有设置为导致任何给定双稳态开关元件切换的小于一概率的参数，以及bi的簇的电阻 - 检测到稳定的开关元件。 注入概率编程电流，并检测到簇状态的电阻，直到满足终止条件。 可选地，终止条件是以表示多位数据的值检测双稳态开关元件群的电阻。

公开(公告)号：US20150071431A1

公开(公告)日：2015-03-12

申请号：US14072634

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  H04L9/30

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1695 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

Abstract: One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.

Abstract translation: 一个特征涉及实现物理不可克隆功能（PUF）的方法。 该方法包括将磁阻随机存取存储器（MRAM）阵列阵列暴露于正交外部磁场。 MRAM单元各自被配置为表示第一逻辑状态和第二逻辑状态之一，并且正交外部磁场定向为与MRAM单元的自由层的容易轴正交的方向，以将MRAM单元置于 不是第一逻辑状态或第二逻辑状态的中性逻辑状态。 该方法还包括去除正交的外部磁场，将阵列的每个MRAM单元随机地置于第一逻辑状态或第二逻辑状态中。

公开(公告)号：US20150071430A1

公开(公告)日：2015-03-12

申请号：US14072599

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  H04L9/30

CPC classification number: G11C11/1673 ,  G09C1/00 ,  G11C11/161 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

Abstract: One feature pertains to a method for implementing a physically unclonable function (PUF). The method includes providing an array of magnetoresistive random access memory (MRAM) cells, where the MRAM cells are each configured to represent one of a first logical state and a second logical state. The array of MRAM cells are un-annealed and free from exposure to an external magnetic field oriented in a direction configured to initialize the MRAM cells to a single logical state of the first and second logical states. Consequently, each MRAM cell has a random initial logical state of the first and second logical states. The method further includes sending a challenge to the MRAM cell array that reads logical states of select MRAM cells of the array, and obtaining a response to the challenge from the MRAM cell array that includes the logical states of the selected MRAM cells of the array.

Abstract translation: 一个特征涉及用于实现物理不可克隆功能（PUF）的方法。 该方法包括提供磁阻随机存取存储器（MRAM）单元阵列，其中MRAM单元被配置为表示第一逻辑状态和第二逻辑状态之一。 MRAM单元的阵列是未退火的，并且没有暴露于被配置为将MRAM单元初始化的方向定向到第一和第二逻辑状态的单个逻辑状态的外部磁场。 因此，每个MRAM单元具有第一和第二逻辑状态的随机初始逻辑状态。 该方法还包括向MRAM单元阵列发送挑战，该MRAM单元阵列读取阵列的选择MRAM单元的逻辑状态，以及从包括阵列的所选MRAM单元的逻辑状态的MRAM单元阵列获得对挑战的响应。

公开(公告)号：US20150056722A1

公开(公告)日：2015-02-26

申请号：US14518459

申请日：2014-10-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Matthew Michael Nowak

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.

Abstract translation: 存储器件可以包括磁性隧道结（MTJ）堆叠，底部电极（BE）层和接触层。 MTJ堆叠可以包括自由层，阻挡层和钉扎层。 BE层可以耦合到MTJ堆叠，并且封装在平坦化层中。 BE层也可以具有与MTJ叠层相当的共同轴。 接触层可以嵌入在BE层中，并且在BE层和MTJ堆叠之间形成界面。

公开(公告)号：US08797792B2

公开(公告)日：2014-08-05

申请号：US14022364

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Hari M. Rao ,  Jung Pil Kim ,  Seung H. Kang ,  Xiaochun Zhu ,  Tae Hyun Kim ,  Kangho Lee ,  Xia Li ,  Wah Nam Hsu ,  Wuyang Hao ,  Jungwon Suh ,  Nicholas K. Yu ,  Matthew Michael Nowak ,  Steven M. Millendorf ,  Asaf Ashkenazi

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/14 ,  G11C17/02 ,  G11C17/16 ,  G11C29/02

CPC classification number: G11C11/16 ,  G11C11/14 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C29/027

Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract translation: 存储器件包括磁性隧道结（MTJ）位单元。 MTJ位单元包括第一MTJ和第二MTJ。 存储器件还包括编程电路，其被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个来在位单元处产生不可逆状态。 不可逆状态对应于通过比较在第一MTJ读取的第一值和在第二MTJ读取的第二值确定的MTJ比特单元的值。

公开(公告)号：US20130040436A1

公开(公告)日：2013-02-14

申请号：US13654245

申请日：2012-10-17

Applicant: QUALCOMM INCORPORATED

Inventor： Matthew Michael Nowak ,  Shiqun Gu

IPC: H01L21/02

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/642 ,  H01L28/60 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

Abstract: A method of manufacturing a semiconductor die having a substrate with a front side and a back side includes fabricating openings for through substrate vias on the front side of the semiconductor die. The method also includes depositing a first conductor in the through substrate vias, depositing a dielectric on the first conductor and depositing a second conductor on the dielectric. The method further includes depositing a protective insulator layer on the back side of the substrate covering the through substrate vias.

Abstract translation: 制造具有正面和背面的基板的半导体管芯的制造方法包括：半导体管芯的正面侧的通过基板通路的制造开口。 该方法还包括在通孔基板通孔中沉积第一导体，在第一导体上沉积电介质并在电介质上沉积第二导体。 该方法还包括在覆盖穿过衬底通孔的衬底的背面上沉积保护绝缘体层。