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公开(公告)号：US10074577B2
公开(公告)日：2018-09-11
申请号：US15220150
申请日：2016-07-26
发明人： Hong He , James Kuss , Nicolas Loubet , Junli Wang
IPC分类号： H01L21/84 , H01L21/8238 , H01L21/02 , H01L21/306 , H01L21/324 , H01L27/092 , H01L27/12 , H01L29/161
CPC分类号： H01L21/845 , H01L21/0217 , H01L21/02532 , H01L21/30604 , H01L21/324 , H01L21/823821 , H01L21/823857 , H01L21/823864 , H01L21/823878 , H01L27/0924 , H01L27/1211 , H01L29/161
摘要： A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.
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52.发明授权公开(公告)号：US09793378B2
公开(公告)日：2017-10-17
申请号：US13906677
申请日：2013-05-31
IPC分类号： H01L29/66 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/7848 , H01L29/785
摘要： Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.
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公开(公告)号：US09640641B2
公开(公告)日：2017-05-02
申请号：US14800381
申请日：2015-07-15
发明人： Hong He , Nicolas Loubet , Junli Wang
IPC分类号： H01L29/66 , H01L21/02 , H01L21/225 , H01L29/78 , H01L29/167
CPC分类号： H01L29/785 , H01L21/02236 , H01L21/02532 , H01L21/02592 , H01L21/2256 , H01L21/31116 , H01L29/1054 , H01L29/161 , H01L29/167 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/66818
摘要： A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.
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54.发明授权公开(公告)号：US09620506B2
公开(公告)日：2017-04-11
申请号：US13907411
申请日：2013-05-31
发明人： Nicolas Loubet , Qing Liu , Prasanna Khare , Stephane Allegret-Maret , Bruce Doris , Kangguo Cheng
IPC分类号： H01L27/088 , H01L27/092 , H01L27/11 , H01L21/8238 , H01L21/84 , H01L29/66 , H01L29/786
CPC分类号： H01L27/092 , H01L21/02164 , H01L21/0217 , H01L21/02532 , H01L21/26513 , H01L21/3065 , H01L21/31111 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823878 , H01L21/84 , H01L27/1104 , H01L27/1116 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/165 , H01L29/41783 , H01L29/6656 , H01L29/66772 , H01L29/78654
摘要： An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.
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公开(公告)号：US20170047406A1
公开(公告)日：2017-02-16
申请号：US15340624
申请日：2016-11-01
发明人： Hong He , Nicolas Loubet , Junli Wang
IPC分类号： H01L29/10 , H01L29/161 , H01L21/225 , H01L21/311 , H01L29/66 , H01L21/02
CPC分类号： H01L29/785 , H01L21/02236 , H01L21/02532 , H01L21/02592 , H01L21/2256 , H01L21/31116 , H01L29/1054 , H01L29/161 , H01L29/167 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/66818
摘要： A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.
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公开(公告)号：US09530777B2
公开(公告)日：2016-12-27
申请号：US14196596
申请日：2014-03-04
发明人： Nicolas Loubet , Hong He , James Kuss
IPC分类号： H01L29/66 , H01L27/088 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L29/165
CPC分类号： H01L27/0886 , H01L21/823418 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Methods and structures for forming finFETs of different semiconductor composition and of different conductivity type on a same wafer are described. Some finFET structures may include strained channel regions. FinFETs of a first semiconductor composition may be grown in trenches formed in a second semiconductor composition. Material of the second semiconductor composition may be removed from around some of the fins at first regions of the wafer, and may remain around fins at second regions of the wafer. A chemical component from the second semiconductor composition may be driven into the fins by diffusion at the second regions to form finFETs of a different chemical composition from those of the first regions. The converted fins at the second regions may include strain.
摘要翻译： 描述了在同一晶片上形成不同半导体组成和不同导电类型的finFET的方法和结构。 一些finFET结构可以包括应变通道区域。 可以在第二半导体组合物中形成的沟槽中生长第一半导体组合物的FinFET。 第二半导体组合物的材料可以从晶片的第一区域周围的一些鳍片周围去除，并且可以保留在晶片的第二区域周围的鳍片周围。 来自第二半导体组合物的化学成分可以通过在第二区域的扩散而被驱入散热片，以形成与第一区域不同的化学组成的finFET。 在第二区域处的转换的翅片可以包括应变。
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公开(公告)号：US09337079B2
公开(公告)日：2016-05-10
申请号：US13647986
申请日：2012-10-09
发明人： Nicolas Loubet , Qing Liu , Shom Ponoth
IPC分类号： H01L21/70 , H01L21/762 , H01L21/84
CPC分类号： H01L21/76283 , H01L21/31111 , H01L21/76232 , H01L21/84
摘要： Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.
摘要翻译： 通过将衬底上的掩埋氧化物覆盖在衬底中以及通过有源硅层上的任何焊盘电介质的有源硅层蚀刻隔离沟槽。 有源硅层的横向外延生长在隔离沟槽中形成至少约5纳米的横向距离的突起，并且围绕突起的部分隔离沟槽被电介质填充。 在包括电介质的有源硅层的部分上形成凸起的源极/漏极区。 结果，穿过凸起的源极/漏极区域的边缘的不对准触点保持与隔离沟槽中的衬底的侧壁间隔开。
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58.发明申请METHOD FOR THE FORMATION OF SILICON AND SILICON-GERMANIUM FIN STRUCTURES FOR FINFET DEVICES 有权用于形成FINFET器件的硅和硅 - 锗晶体结构的方法公开(公告)号：US20160035872A1
公开(公告)日：2016-02-04
申请号：US14449192
申请日：2014-08-01
发明人： Nicolas Loubet , Hong He , James Kuss
CPC分类号： H01L29/785 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795
摘要： A substrate layer formed of a first semiconductor material includes adjacent first and second regions. Fin structures are formed from the substrate layer in both the first and second regions. At least the side walls of the fin structures in the second region are covered with an epitaxially grown layer of second semiconductor material. A drive in process is performed to convert the fin structures in the second region from the first semiconductor material to the second semiconductor material. The first semiconductor material is, for example, silicon, and the second semiconductor material is, for example, silicon germanium or silicon carbide. The fin structures in the first region are provided for a FinFET of a first (for example, n-channel) conductivity type while the fin structures in the second region are provided for a FinFET of a second (for example, p-channel) conductivity type.
摘要翻译： 由第一半导体材料形成的衬底层包括相邻的第一和第二区域。 翅片结构由第一和第二区域中的基底层形成。 至少第二区域中的翅片结构的侧壁被外延生长的第二半导体材料层覆盖。 执行处理中的驱动以将第二区域中的鳍状结构从第一半导体材料转换成第二半导体材料。 第一半导体材料是例如硅，第二半导体材料是例如硅锗或碳化硅。 第一区域中的鳍结构被提供用于第一（例如，n沟道）导电类型的FinFET，而第二区域中的翅片结构被设置用于具有第二（例如，p沟道）导电性的FinFET 类型。
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公开(公告)号：US20160013096A1
公开(公告)日：2016-01-14
申请号：US14856949
申请日：2015-09-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , STMicroelectronics, Inc. , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
IPC分类号： H01L21/762 , H01L21/768 , H01L29/06 , H01L29/417 , H01L29/08 , H01L21/02 , H01L29/66
CPC分类号： H01L21/76879 , H01L21/0217 , H01L21/76224 , H01L21/76283 , H01L21/76802 , H01L21/76877 , H01L21/76897 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/41783 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66628 , H01L29/78609
摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
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公开(公告)号：US20150325487A1
公开(公告)日：2015-11-12
申请号：US14802407
申请日：2015-07-17
IPC分类号： H01L21/84 , H01L21/02 , H01L29/66 , H01L21/8238 , H01L21/762
CPC分类号： H01L21/845 , H01L21/02529 , H01L21/02532 , H01L21/76224 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/6653 , H01L29/6656
摘要： On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.
摘要翻译： 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。
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