公开(公告)号：US20160005831A1

公开(公告)日：2016-01-07

申请号：US14320831

申请日：2014-07-01

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L29/49 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

Abstract: Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

Abstract translation: 硅 - 锗表面层在半导体表面上的选择性沉积可用于为场效应晶体管提供两种类型的沟道区。 在硅基栅极电介质和高介电常数（高k）栅极电介质的堆叠上的调整氧化物材料的退火可以用于形成接触通道区域子集的界面调整氧化物层。 通过沉积第一功函数金属材料层和封盖层和随后的退火，可以在覆盖界面调整氧化物层的高k电介质层的部分中诱导氧缺乏。 可以通过物理暴露高k电介质层的部分来选择性地去除氧缺乏。 可以将第二功函数金属材料层和栅极导体层沉积并平坦化以形成提供多个有效功函数的栅电极。

公开(公告)号：US20150380438A1

公开(公告)日：2015-12-31

申请号：US14315362

申请日：2014-06-26

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Ramachandra Divakaruni ,  Judson R. Holt ,  Arvind Kumar ,  Unoh Kwon

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L27/1207 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.

Abstract translation: 本发明一般涉及半导体器件，更具体地说，涉及通过捕获外延期间发生的晶格位错而在绝缘体上硅绝缘体（SOI）衬底上形成高迁移率鳍状场效应晶体管（finFET）鳍的结构和方法 在半导体层中形成的凹部中生长。 结晶晶格位错可以保留在薄的隔离层下方，从而减少器件厚度以及高纵横比蚀刻和鳍形成的需要。

公开(公告)号：US20150228747A1

公开(公告)日：2015-08-13

申请号：US14179074

申请日：2014-02-12

Applicant: International Business Machines Corporation

Inventor： Unoh Kwon ,  Wing L. Lai ,  Vijay Narayanan ,  Sean M. Polvino ,  Ravikumar Ramachandran ,  Shahab Siddiqui

IPC: H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/513 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545

Abstract: After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.

Abstract translation: 在去除一次性栅极结构以在平坦化介电层中形成栅极空腔之后，氧化硅层被共形沉积在栅极腔中的基于氧化硅的栅极电介质部分上。 氧化硅层的一部分可以被氮化以形成氮氧化硅层。 可以使用图案化的掩模材料层来物理地暴露半导体表面从第一类型的门腔。 可以除去氧化硅层，同时在第二型栅极腔中保留下面的基于氧化硅的栅极电介质部分。 在去除第二类型栅腔中的氧化硅层时，可以通过第三型栅极腔中的图案化掩模材料层来保护硅氮氧化物层和下面的基于氧化硅的栅极电介质的堆叠。 可以在栅极腔中形成高介电常数栅极电介质层，以提供不同类型的栅极电介质。

公开(公告)号：US09087722B2

公开(公告)日：2015-07-21

申请号：US14541182

申请日：2014-11-14

Applicant: International Business Machines Corporation

Inventor： Charlotte D. Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC: H01L29/02 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

Abstract translation: 制造具有不同厚度栅极氧化物的多个finFET器件的方法。 该方法可以包括在半导体衬底的顶部上，在第一鳍的顶部上并在第二鳍的顶部上沉积第一介电层; 形成第一虚拟栅极堆叠; 形成第二虚拟栅极叠层; 去除对第一和第二栅极氧化物选择性的第一和第二伪栅极; 掩蔽包括第二鳍片的半导体结构的一部分，并且从第一鳍片顶部去除第一栅极氧化物; 以及在所述第一开口内沉积第二电介质层，并且在所述第二开口内，所述第二电介质层位于所述第一散热片的顶部并且邻近所述第一对电介质间隔件的暴露的侧壁，并且在所述第二栅极的顶部 氧化物并且与第二对电介质间隔物的暴露的侧壁相邻。

公开(公告)号：US09006837B2

公开(公告)日：2015-04-14

申请号：US13793682

申请日：2013-03-11

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A complementary metal oxide semiconductor structure including a scaled 0 and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and an nFET threshold voltage adjusted species, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and a pFET threshold voltage adjusted species.

Abstract translation: 提供了包括缩放的0和在操作期间不表现出增加的阈值电压和降低的移动性的定标pFET的互补金属氧化物半导体结构。 该方法包括在nFET栅极堆叠内形成等离子体氮化nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以是等离子体氮化的。 等离子体氮化，nFET阈值电压调节的高k栅极电介质层部分包含高达15原子％的N 2和nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分含有高达15原子％ N2和pFET阈值电压调整种。

公开(公告)号：US08901674B2

公开(公告)日：2014-12-02

申请号：US13775430

申请日：2013-02-25

Applicant: International Business Machines Corporation

Inventor： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon ,  Christopher Carr Parks ,  Yun-Yu Wang

IPC: H01L21/02 ,  H01L29/02 ,  H01L21/70 ,  H01L21/8238 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

Abstract: A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

Abstract translation: 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。

公开(公告)号：US20130277767A1

公开(公告)日：2013-10-24

申请号：US13780957

申请日：2013-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

IPC: H01L29/51

CPC classification number: H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

Abstract: A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

Abstract translation: 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

公开(公告)号：US20130260549A1

公开(公告)日：2013-10-03

申请号：US13771937

申请日：2013-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

IPC: H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.

Abstract translation: 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括与其它层组合提供约4.4eV或更低的功函数的材料，并且可以包括选自碳化钽，金属氮化物和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。 任选地，可以在通道中引入碳掺杂。

公开(公告)号：US20130217219A1

公开(公告)日：2013-08-22

申请号：US13842217

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

Abstract translation: 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

公开(公告)号：US20130187239A1

公开(公告)日：2013-07-25

申请号：US13793682

申请日：2013-03-11

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC: H01L27/092

CPC classification number: H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A complementary metal oxide semiconductor structure including a scaled nFET and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and an nFET threshold voltage adjusted species, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and a pFET threshold voltage adjusted species.

Abstract translation: 提供了包括缩放的nFET和定标pFET的互补金属氧化物半导体结构，其在操作期间不表现出增加的阈值电压和降低的迁移率。 该方法包括在nFET栅极堆叠内形成等离子体氮化nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以是等离子体氮化的。 等离子体氮化，nFET阈值电压调节的高k栅极电介质层部分包含高达15原子％的N 2和nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分含有高达15原子％ N2和pFET阈值电压调整种。